초록 ▼

A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures

A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g., Co—Ge or Ti—Ge, two annealing steps are required to provide the lowest resistance phase of those metals, whereas, when Ni is employed, a single annealing step forms the lowest resistance phase of Ni silicide.

대표청구항 ▼

1. An electrical contact to a region of a silicon-containing substrate comprising:a substrate having an exposed region of a silicon-containing semiconductor material; anda first layer of metal disilicide which includes an additive or Ge, wherein said metal of said disilicide is selected from the sou

1. An electrical contact to a region of a silicon-containing substrate comprising:a substrate having an exposed region of a silicon-containing semiconductor material; anda first layer of metal disilicide which includes an additive or Ge, wherein said metal of said disilicide is selected from the soup consisting of Ti, Co and mixtures thereof, and said exposed region of said substrate and said first layer are separated by a Si—Ge interlayer, wherein said Si—Ge interlayer has a thickness less than about 3.0 nm. 2. The electrical contact of claim 1 wherein said silicon-containing semiconductor material comprises single crystal Si, polycrystalline Si, SiGe, amorphous Si or a silicon-on-insulator (SOI). 3. The electrical contact of claim 1 wherein said metal of said disilicide is Co and said metal silicide is Co disilicide. 4. The electrical contact of claim 1 wherein said metal of said disilicide is Ti and said metal silicide is TiSi 2 . 5. The electrical contact of claim 4 wherein said TiSi 2 is in the C54 phase. 6. The electrical contact of claim 1 wherein said substrate is doped. 7. The electrical contact of claim 1 wherein said additive is selected from the group consisting of C, Al, Si, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Y, Zr, Nb, Mo, Ru, Rh, Pd, In, Sn, La, Hf, Ta, W, Re, Ir, Pt, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and mixtures thereof. 8. The electrical contact of claim 7 wherein said additive is C, Al, Si, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Y, Zr, Nb, Mo, Ru, Rh, Pd, In, Sn, La, Hf, Ta, W, Re, Ir, Pt or mixtures thereof. 9. The electrical contact of claim 8 wherein said additive is Si, Ti, V, Cr, Ni, Nb, Rb, Ta, Re, Ir or mixtures thereof. 10. The electrical contact of claim 1 wherein said additive is present in said metal disilicide in an amount of from about 0.01 to about 50 atomic percent. 11. An electrical contact to a region of a silicon-containing substrate comprising:a substrate having an exposed region of a silicon-containing semiconductor material; anda first layer of metal disilicide, wherein said metal of said disilicide is selected from the group consisting of Ti, Co and mixtures thereof, and said exposed region of said substrate and said first layer are separated by a Si—Ge interlayer positioned on an interface between said first layer and said substrate, wherein said Si—Ge interlayer does not substantially extend beyond said interface.