초록 ▼

It is intended to prevent a crack from occurring in a circuit region during dicing, while preventing oxidation and corrosion of a seal ring including a layer of copper as the uppermost layer thereof.A passivation film ( 120 ) has an opening ( 123 ) formed therein, The opening ( 123 ) is formed so as

It is intended to prevent a crack from occurring in a circuit region during dicing, while preventing oxidation and corrosion of a seal ring including a layer of copper as the uppermost layer thereof.A passivation film ( 120 ) has an opening ( 123 ) formed therein, The opening ( 123 ) is formed so as to reach an interlayer insulating film ( 109 ) and disposed so as to surround a periphery of a seal ring ( 110 ). As a result, a top face of a second interconnect layer ( 114 ) is completely covered by the passivation film ( 120 ), and is not exposed to an ambient air. Hence, it is possible to prevent an effect of protecting a semiconductor device achieved by the seal ring ( 110 ) from being reduced due to oxidation and corrosion of the second interconnect layer ( 114 ). Further, provision of the opening ( 123 ) does not allow a stress generated at a time of cutting a dicing region during dicing to easily propagate to a portion of the passivation film ( 120 ) present on the circuit region. This prevents occurrence of a crack in the circuit region.

대표청구항 ▼

1. A semiconductor device comprising:a seal ring formed in a vicinity of an edge portion of a semiconductor chip so as to surround a circuit region of said semiconductor chip;a first passivation film formed above said seal ring so as to cover a surface of said semiconductor chip, said first passivat

1. A semiconductor device comprising:a seal ring formed in a vicinity of an edge portion of a semiconductor chip so as to surround a circuit region of said semiconductor chip;a first passivation film formed above said seal ring so as to cover a surface of said semiconductor chip, said first passivation film having a first opening reaching a top face of an uppermost layer of said seal ring;an aluminum interconnect layer formed in said first opening; anda second passivation film formed so as to cover said first passivation film and said aluminum interconnect layer, said second passivation film having an etch selectivity relative to said first passivation film,wherein said second passivation film has a second opening reaching a top face of said first passivation film, andsaid second opening does not penetrate said first passivation film. 2. The semiconductor device according to claim 1,wherein said uppermost layer of said seal ring is made of copper.