$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Method of preparing a semiconductor having controlled crystal orientation 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-031/036
출원번호 US-0238579 (1999-01-28)
우선권정보 JP-0180752 (1993-06-25); JP-0036616 (1994-02-08)
발명자 / 주소
  • Zhang, Hongyong
  • Takayama, Toru
  • Takemura, Yasuhiko
  • Miyanaga, Akiharu
  • Ohtani, Hisashi
  • Takeyama, Junichi
출원인 / 주소
  • Semiconductor Energy Laboratory Co., Ltd.
대리인 / 주소
    Robinson Eric J.
인용정보 피인용 횟수 : 87  인용 특허 : 21

초록

A semiconductor device is disclosed. The semiconductor device has a crystalline silicon film as an active layer region. The crystalline silicon film has needle-like or columnar crystals oriented parallel to the substrate and having a crystal growth direction of ( 111 ) axis. A method for preparing t

대표청구항

1. A semiconductor device comprising:a crystalline semiconductor film comprising silicon provided over a substrate and containing a crystallization-promoting element,wherein the crystal growth face is the face ( 111 ). 2. The device of claim 1 wherein the crystallization-promoting element comprises

이 특허에 인용된 특허 (21)

  1. See Yee-Chaung (Austin TX) Mele Thomas C. (Austin TX) Alvis John R. (Austin TX), BiCMOS device having an SOI substrate and process for making the same.
  2. Lin Albert M. (Allentown PA), Controlled boron doping of silicon.
  3. Tsubone Ko (Tokyo JPX) Umemura Yoshio (Tokyo JPX) Shimoda Kouichi (Tokyo JPX), Fabrication method for BiMOS semiconductor devices with improved speed and reliability.
  4. Thibault Louis R. (Piscataway NJ) Yau Leopoldo D. (New Providence NJ), Fabrication of small contact openings in large-scale-integrated devices.
  5. Iyer Subramanian S. (Yorktown Heights NY) Thompson Richard D. (Lake Peekskill NY) Tu King-Ning (Chappaqua NY), Formation of 3-dimensional silicon silicide structures.
  6. Liu Gang (State College PA) Kakkad Ramesh H. (State College PA) Fonash Stephen J. (State College PA), Low temperature crystallization and pattering of amorphous silicon films.
  7. Fonash Stephen J. (State College PA) Liu Gang (Sunnyvale CA), Low temperature crystallization and patterning of amorphous silicon films on electrically insulating substrates.
  8. Yonehara Takao (Atsugi JPX), Method for forming semiconductor thin film.
  9. Noguchi Takashi (Kanagawa JPX) Hayashi Hisao (Kanagawa JPX) Ohshima Takefumi (Kanagawa JPX), Method of forming a thin semiconductor film.
  10. Fu Horng-Sen (Sunnyvale CA) Moll John L. (Palo Alto CA) Manoliu Juliana (Palo Alto CA), Method of forming self-registering source, drain, and gate contacts for FET transistor structures.
  11. Zhang Hongyong,JPX ; Takayama Toru,JPX ; Takemura Yasuhiko,JPX ; Miyanaga Akiharu,JPX ; Ohtani Hisashi,JPX ; Takeyama Junichi,JPX, Method of preparing a semiconductor having a controlled crystal orientation.
  12. Burgener Mark L. (San Diego CA) Reedy Ronald E. (San Diego CA), Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer.
  13. Miyasaka Mitsutoshi (Suwa JPX) Little Thomas W. (Suwa JPX), Process for fabricating a thin film semiconductor device.
  14. Shirai Shigeru (Nagahama JPX), Process for photo-assisted epitaxial growth using remote plasma with in-situ etching.
  15. Sugahara Kazuyuki (Hyogo JPX) Nishimura Tadashi (Hyogo JPX) Kusunoki Shigeru (Hyogo JPX) Inoue Yasuo (Hyogo JPX), Process for producing single crystal semiconductor layer and semiconductor device produced by said process.
  16. Akiharu Mitanaga JP; Hisashi Ohtani JP; Satoshi Teramoto JP, Semiconductor device.
  17. Yamazaki Shunpei (Tokyo JPX) Mase Akira (Aichi JPX) Hiroki Masaaki (Kanagawa JPX) Takemura Yasuhiko (Kanagawa JPX) Zhang Hongyong (Kanagawa JPX) Uochi Hideki (Kanagawa JPX), Semiconductor device and method for forming the same.
  18. Zhang Hongyong,JPX ; Takemura Yasuhiko,JPX ; Takayama Toru,JPX ; Miyanaga Akiharu,JPX ; Ohtani Hisashi,JPX ; Takeyama Junichi,JPX, Semiconductor device and method for its preparation.
  19. Aoyama Takashi (Ibaraki JPX) Konishi Nobutake (Hitachiota JPX) Suzuki Takaya (Katsuta JPX) Miyata Kenji (Katsuta JPX) Oikawa Saburo (Hitachi JPX) Okajima Yoshiaki (Ibaraki JPX) Kawachi Genshiro (Hita, Thin film semiconductor device and method for fabricating the same.
  20. Konishi Nobutake (Hitachiota JPX) Hosokawa Yoshikazu (Hitachiota JPX) Mimura Akio (Katsuta JPX) Suzuki Takaya (Katsuta JPX) Ohwada Jun-ichi (Hitachi JPX) Kawakami Hideaki (Mito JPX) Miyata Kenji (Kat, Thin film semiconductor device and method of manufacturing the same.
  21. Zhang Hongyong (Paresu Miyagami 302 1-10-15 ; Fukamidai ; Yamato-shi ; Kanagawa-ken 242 JPX) Yamazaki Shunpei (21-21 ; Kitakarasuyama ; 7-chome Setagaya-ku ; Tokyo 157 JPX), Thin-film transistor.

이 특허를 인용한 특허 (87)

  1. Radosavljevic,Marko; Majumdar,Amlan; Doyle,Brian S.; Kavalieros,Jack; Doczy,Mark L.; Brask,Justin K.; Shah,Uday; Datta,Suman; Chau,Robert S., Block contact architectures for nanoscale channel transistors.
  2. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  3. Lindert,Nick; Cea,Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  4. Lindert,Nick; Cea,Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  5. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  6. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
  7. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  8. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  9. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  10. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  11. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  12. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  13. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  14. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  15. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  16. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  17. Shaheen,Mohamad A.; Doyle,Brian; Dutta,Suman; Chau,Robert S.; Tolchinsky,Peter, High mobility tri-gate devices and methods of fabrication.
  18. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  19. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  20. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  21. Datta,Suman; Brask,Justin K.; Kavalieros,Jack; Doyle,Brian S.; Dewey,Gilbert; Doczy,Mark L.; Chau,Robert S., Lateral undercut of metal gate in SOI device.
  22. Tateishi, Fuminori, Manufacturing method of micro-electro-mechanical device.
  23. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  24. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  25. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  26. Izumi, Konami; Yamaguchi, Mayumi, Method for manufacturing semiconductor device including microstructure.
  27. Shah,Uday; Doyle,Brian S.; Brask,Justin K.; Chau,Robert S., Method of fabricating a multi-cornered film.
  28. Brask,Justin K.; Doyle,Brian S.; Kavalleros,Jack; Doczy,Mark; Shah,Uday; Chau,Robert S., Method of forming a metal oxide dielectric.
  29. Brask, Justin K.; Doyle, Brian S.; Kavalieros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material.
  30. Doyle,Brian S.; Datta,Suman; Kavalieros,Jack T.; Majumdar,Amlan, Method of ion implanting for tri-gate devices.
  31. Takano, Tamae, Method of manufacturing a semiconductor device.
  32. Yamazaki,Shunpei; Ohtani,Hisashi; Ohnuma,Hideto, Method of manufacturing a semiconductor device.
  33. Yamaguchi, Mayumi; Izumi, Konami, Method of manufacturing micromachine having spatial portion within.
  34. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  35. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
  36. Yamaguchi, Mayumi; Izumi, Konami, Micromachine and method for manufacturing the same.
  37. Yamaguchi, Mayumi; Izumi, Konami, Micromachine and method for manufacturing the same.
  38. Zhang,Yuegang; Doyle,Brian S.; Bourianoff,George I., Multi-gate carbon nano-tube transistors.
  39. Doyle, Brian S.; Datta, Suman; Jin, Been Yih; Chau, Robert, Non-planar MOS structure with a strained channel region.
  40. Doyle,Brian S.; Datta,Suman; Jin,Been Yih; Chau,Robert, Non-planar MOS structure with a strained channel region.
  41. Doyle,Brian S; Datta,Suman; Jin,Been Yih; Zelick,Nancy M; Chau,Robert, Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow.
  42. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Datta,Suman; Jin,Been Yih, Nonplanar device with stress incorporation layer and method of fabrication.
  43. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  44. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  45. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  46. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  47. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  48. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  49. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  50. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  51. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  52. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Rios,Rafael; Linton,Tom; Datta,Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  53. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
  54. Brask,Justin K.; Doyle,Brian S.; Doczy,Mark L.; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
  55. Brask,Justin K.; Doyle,Brian S.; Kavalieros,Jack; Doczy,Mark; Shah,Uday; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
  56. Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  57. Kavalieros,Jack T.; Brask,Justin K.; Doyle,Brian S.; Shah,Uday; Datta,Suman; Doczy,Mark L.; Metz,Matthew V.; Chau,Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  58. Izumi, Konami; Yamaguchi, Mayumi, Semiconductor device.
  59. Miyanaga, Akiharu; Ohtani, Hisashi; Takemura, Yasuhiko, Semiconductor device and method for manufacturing the same.
  60. Miyanaga,Akiharu; Ohtani,Hisashi; Takemura,Yasuhiko, Semiconductor device and method for manufacturing the same.
  61. Hayakawa, Masahiko, Semiconductor device and method of fabricating the same.
  62. Hayakawa, Masahiko, Semiconductor device and method of fabricating the same.
  63. Yamazaki, Shunpei; Ohtani, Hisashi; Koyama, Jun; Fukunaga, Takeshi, Semiconductor device and method of manufacturing the same.
  64. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  65. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  66. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  67. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  68. Kakehata, Tetsuya, Semiconductor device, manufacturing method thereof, liquid crystal display device, RFID tag, light emitting device, and electronic device.
  69. Yamazaki, Shunpei; Ohtani, Hisashi; Mitsuki, Toru; Miyanaga, Akiharu; Ogata, Yasushi, Semiconductor thin film and semiconductor device.
  70. Yamazaki, Shunpei; Ohtani, Hisashi; Mitsuki, Toru; Miyanaga, Akiharu; Ogata, Yasushi, Semiconductor thin film and semiconductor device.
  71. Yamazaki,Shunpei; Ohtani,Hisashi; Mitsuki,Toru; Miyanaga,Akiharu; Ogata,Yasushi, Semiconductor thin film and semiconductor device.
  72. Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
  73. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  74. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  75. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  76. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  77. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  78. Hatano,Mutsuko; Yamaguchi,Shinya; Kimura,Yoshinobu; Park,Seong Kee, Thin film semiconductor device, polycrystalline semiconductor thin film production process and production apparatus.
  79. Chau, Robert S.; Doyle, Brian S.; Kavalieros, Jack; Barlage, Douglas; Datta, Suman, Tri-gate devices and methods of fabrication.
  80. Chau, Robert S.; Doyle, Brian S.; Kavalieros, Jack; Barlage, Douglas; Datta, Suman; Hareland, Scott A., Tri-gate devices and methods of fabrication.
  81. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman, Tri-gate devices and methods of fabrication.
  82. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman, Tri-gate devices and methods of fabrication.
  83. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman; Hareland,Scott A., Tri-gate devices and methods of fabrication.
  84. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  85. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  86. Chau,Robert; Datta,Suman; Doyle,Brian S; Jin,Been Yih, Tri-gate transistors and methods to fabricate same.
  87. Shaheen, Mohamad A.; Rachmady, Willy; Tolchinsky, Peter, Ultra-thin oxide bonding for S1 to S1 dual orientation bonding.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로