초록 ▼

A cross-pin electro-static-discharge (ESD) protection device protects against ESD zaps between two I/O pins. Pin A is connected to a drain of a bus-switch transistor and pin B is connected to the transistor's source. An ESD protection device on pin A has an n-channel shunting transistor to an intern

A cross-pin electro-static-discharge (ESD) protection device protects against ESD zaps between two I/O pins. Pin A is connected to a drain of a bus-switch transistor and pin B is connected to the transistor's source. An ESD protection device on pin A has an n-channel shunting transistor to an internal ground bus. The gate of the shunting transistor is a cross-gate node that is capacitivly coupled to pin A, and has a leaker resistor to ground. An n-channel cross-grounding transistor has its gate connected to the same cross-gate node, but it connects the internal ground bus to pin B, which is grounded in the pin-to-pin ESD test. An ESD pulse on pin A drives the cross-gate node high, turning on both the shunting transistor and the cross-grounding transistor. The floating internal ground bus is connected to ground by pin B, grounding the substrate of the bus-switch transistor to prevent its turn-on.

대표청구항 ▼

1. A cross-pin electro-static-discharge (ESD) protection device comprising:a first pad, connected to a first internal node, for connecting to an external device, the first pad receiving a positive ESD pulse during a pin-to-pin ESD test;a second pad, connected to a second internal node, for connectin

1. A cross-pin electro-static-discharge (ESD) protection device comprising:a first pad, connected to a first internal node, for connecting to an external device, the first pad receiving a positive ESD pulse during a pin-to-pin ESD test;a second pad, connected to a second internal node, for connecting to an external device, the second pad receiving an ESD ground during the pin-to-pin ESD test;an internal ground bus, connected to a ground pad but not connected to the first or second pad, wherein the internal ground bus is floating during the pin-to-pin ESD test;a first shunting transistor, coupled to shunt ESD current from the first internal node to the internal ground bus when the positive ESD pulse is applied to the first pad;a coupling capacitor, coupled between the first internal node and a cross-gate node, for charging the cross-gate node when the positive ESD pulse is applied to the first pad; anda first grounding transistor, being activated by the cross-gate node, for connecting the internal ground bus to the second internal node to dynamically apply the ESD ground to the internal ground bus during the pin-to-pin ESD test;whereby the internal ground bus is grounded to the second pad by the first grounding transistor, while ESD current from the first pad is shunted to the internal ground bus by the first shunting transistor. 2. The cross-pin ESD protection device of claim 1 wherein the cross-gate node connects to a gate of the first shunting transistor and to a gate of the first grounding transistor,whereby the first shunting transistor and the first grounding transistor share a common gate node, even though current is conducted from different pads. 3. The cross-pin ESD protection device of claim 2 wherein the first shunting transistor is an n-channel transistor and the first grounding transistor is an n-channel transistor. 4. The cross-pin ESD protection device of claim 3 further comprising:a leaker resistor, coupled between the cross-gate node and the internal ground bus,whereby the cross-gate node is discharged by the leaker resistor. 5. The cross-pin ESD protection device of claim 3 further comprising:a bus-switch transistor coupled to conduct current between the first internal node and the second internal node during normal operation, but for isolating the first internal node from the second internal node during the pin-to-pin ESD test;whereby the bus-switch transistor is protected from the positive ESD pulse by the first shunting transistor. 6. The cross-pin ESD protection device of claim 5 wherein the bus-switch transistor is an n-channel transistor having a substrate coupled to the internal ground bus;whereby the substrate of the bus-switch transistor is biased to the ESD ground by the first grounding transistor and the internal ground bus during the pin-to-pin ESD test. 7. The cross-pin ESD protection device of claim 6 wherein an n-type source, the substrate which is p-type, and an n-type drain of the bus-switch transistor form a parasitic NPN transistor;wherein a breakdown voltage of the parasitic NPN transistor of the bus-switch transistor is made more positive by the first grounding transistor connecting the substrate to the ESD ground during the pin-to-pin ESD test. 8. The cross-pin ESD protection device of claim 5 further comprising:a second shunting transistor, coupled to shunt ESD current from the second internal node to the internal ground bus when the positive ESD pulse is applied to the second pad;a second coupling capacitor, coupled between the second internal node and a reverse cross-gate node, for charging the reverse cross-gate node when the positive ESD pulse is applied to the second pad; anda second grounding transistor, being activated by the reverse cross-gate node, for connecting the internal ground bus to the first internal node to dynamicallyapply the ESD ground to the internal ground bus during a reverse pin-to-pin ESD test;whereby the internal ground bus is grounded to the first pad by the second grounding transistor, while ESD current from the second pad is shunted to the internal ground bus by the second shunting transistor. 9. The cross-pin ESD protection device of claim 8 wherein the second shunting transistor and the second grounding transistors are n-channel transistors having gates connected to the reverse cross-gate node. 10. The cross-pin ESD protection device of claim 9 further comprising:a second leaker resistor, coupled between the reverse cross-gate node and the internal ground bus. 11. A bus-switch chip comprising:a first input;a second input;an internal bus that is isolated from the first and second inputs;bus-switch transistor means for conducting current between the first input and the second input when activated by an enable signal during normal operation;first coupling means for coupling a portion of a first voltage shock applied to the first input to a first activating node;first shunting means, responsive to the first activating node, for shunting current from the first input to the internal bus when the first coupling means couples the portion of the first voltage shock to the first activating node; andfirst clamping means, responsive to the first activating node, for clamping the internal bus to the second input when the first coupling means couples the portion of the first voltage shock to the first activating node,whereby the first shunting means and the first clamping means are activated by the first activating node. 12. The bus-switch chip of claim 11 further comprising:second coupling means for coupling a portion of a second voltage shock applied to the second input to a second activating node;second shunting means, responsive to the second activating node, for shunting current from the second input to the internal bus when the second coupling means couples the portion of the second voltage shock to the second activating node; andsecond clamping means, responsive to the second activating node, for clamping the internal bus to the first input when the second coupling means couples the portion of the second voltage shock to the second activating node,whereby the second shunting means and the second clamping means are activated by the second activating node. 13. The bus-switch chip of claim 12 wherein the second clamping means comprises a second n-channel transistor means for conducting current between the first input and the internal bus when the second activating node receives the portion of the second voltage shock, wherein the first activating node is a gate of the second n-channel transistor means. 14. The bus-switch chip of claim 13 wherein the first shunting means comprises a third n-channel transistor means for conducting current between the first input and the internal bus when the first activating node receives the portion of the first voltage shock, wherein the first activating node is a gate of the third n-channel transistor means;wherein the second shunting means comprises a fourth n-channel transistor means for conducting current between the second input and the internal bus when the second activating node receives the portion of the second voltage shock, wherein the second activating node is a gate of the fourth n-channel transistor means. 15. The bus-switch chip of claim 14 wherein the bus-switch transistor means comprises a fifth n-channel transistor means for conducting current between the first input and the second input, wherein the enable signal is a gate of the fifth n-channel transistor means;wherein the internal bus is a ground bus that connects to a substrate under the fifth n-channel transistor means. 16. The bus-switch chip of claim 15 wherein the first and second coupling means comprise capacitors, further comprising:first leaker means, coupled to the first activating node, for leaking charge from the first activating node to the internal bus;second leaker means, coupled to the second activating node, for leaking charge from the second activating node to the i nternal bus. 17. An electro-static-discharge (ESD) protection circuit comprising:an internal bus;a bus-switch transistor having a gate driven by an enable signal, a drain coupled to a first input, a source coupled to a second input, and a substrate coupled to the internal bus by substrate taps;a first capacitor between the first input and a first gate node;a first shunt transistor having the first gate node as its gate, a drain coupled to the first input and a source coupled to the internal bus;a first remote transistor having the first gate node as its gate, a drain coupled to the second input and a source coupled to the internal bus. 18. The ESD protection circuit of claim 17 further comprising:a second capacitor between the second input and a second gate node;a second shunt transistor having the second gate node as its gate, a drain coupled to the second input and a source coupled to the internal bus;a second remote transistor having the second gate node as its gate, a drain coupled to the first input and a source coupled to the internal bus. 19. The ESD protection circuit of claim 18 further comprising:a first resistor coupled between the first gate node and the internal bus;a second resistor coupled between the second gate node and the internal bus. 20. The ESD protection circuit of claim 17 wherein the bus-switch transistor is an n-channel transistor, the first and second shunt transistors are n-channel transistors and the first and second remote transistors are n-channel transistors.