[특허]Method of constructing a capacitor stack for a flat capacitor

[미국특허] Method of constructing a capacitor stack for a flat capacitor 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	A61N-001/02 H01G-009/022
출원번호	US-0418616 (2003-04-17)
발명자 / 주소	O'Phelan, Michael J. Poplett, James M. Tong, Robert R. Barr, A. Gordon Kavanagh, Richard J. Waytashek, Brian V.
출원인 / 주소	Cardiac Pacemakers, Inc.
대리인 / 주소	Schwegman, Lundberg, Woessner & Kluth, P.A.
인용정보	피인용 횟수 : 37 인용 특허 : 84

초록 ▼

In one aspect, a method of manufacturing a capacitor includes disposing one or more conductive layers of a first electrode stack in a recess of an alignment mechanism, where the recess is positioned relative to two or more alignment elements. The method further includes placing a separator over the one or more conductive layers where an outer edge of the separator contacts the two or more alignment elements. In one embodiment, a capacitor includes anode and cathode foils having offsetting edge portions. In one embodiment, a multiple tab cathode for a flat capacitor. A plurality of cathode tabs are portioned into a plurality of cathode tab groups positioned in different locations along the edge of the capacitor stack to reduce the amount of space required for connecting and routing the cathode tabs.

대표청구항 ▼

1. A method of manufacturing a flat capacitor stack, comprising:forming a plurality of capacitor layers, each capacitor layer including a separator layer attached to a capacitor foil layer; andplacing each of the plurality of capacitor layers onto a capacitor stack by aligning each of the capacitor layers using an outer edge of the separator layer of the capacitor layer as an alignment means. 2. The method of claim 1, wherein aligning includes positioning the separator layer such that two or more points on an outer edge of the separator layer contact two or more corresponding alignment members. 3. The method of claim 1, further comprising pressing the capacitor stack to a specified, predetermined height after the capacitor stack has been formed. 4. The method of claim 1, further comprising annealing the capacitor stack after the capacitor stack has been formed. 5. The method of claim 1, wherein placing each of the plurality of capacitor layers includes:providing an alignment mechanism; andplacing each capacitor layer within the alignment mechanism such that an outer edge of each separator layer contacts one or more alignment members of the alignment mechanism. 6. The method of claim 1, wherein forming a plurality of capacitor layers includes forming a first anode stack having or more anode layers and having a first surface area, and forming a second anode stack having or more anode layers and having a second surface area, wherein the first surface area is greater than the second surface area. 7. The method of claim 6, wherein the second anode stack has one or more less anode layers than the first anode stack. 8. A flat capacitor having a capacitor stack formed by a method including:forming a plurality of capacitor layers, each capacitor layer including a separator layer attached to a capacitor foil layer; andplacing each of the plurality of capacitor layers onto a capacitor stack by aligning each of the capacitor layers using an outer edge of the separator layer of the capacitor layer as an alignment means. 9. The flat capacitor of claim 8, wherein aligning the separator layer includes positioning the separator layer such that two or more points on an outer edge of the separator layer contact two or more corresponding two or more alignment members. 10. The flat capacitor of claim 8, further comprising pressing the capacitor stack to a specified, predetermined height. 11. The flat capacitor of claim 8, further comprising annealing the capacitor stack. 12. The flat capacitor of claim 8, wherein aligning each of the plurality of capacitor layers includes:providing an alignment mechanism; andplacing each capacitor layer within the alignment mechanism such that an outer edge of each separator layer contacts one or more alignment members of the alignment mechanism. 13. The flat capacitor of claim 8, wherein at least one of the plurality of capacitor layers includes a first anode stack having or more anode layers and having a first surface area, and wherein at least one of the plurality of capacitor layers includes a second anode stack having or more anode layers and having a second surface area, wherein the first surface area is greater than the second surface area. 14. The flat capacitor of claim 13, wherein the second anode stack has one or more less anode layers than the first anode stack.

이 특허에 인용된 특허 (84) 인용/피인용 타임라인 분석

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이 특허를 인용한 특허 (37) 인용/피인용 타임라인 분석

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해당 특허가 속한 카테고리에서 활용도가 높은 상위 5개 콘텐츠를 보여줍니다.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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[미국특허] Method of constructing a capacitor stack for a flat capacitor 원문보기

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[미국특허] Method of constructing a capacitor stack for a flat capacitor 원문보기

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