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A scrambler includes a linear shift register having logic suitable for generating a scrambling sequence according to a predetermined generator sequence, a plurality of logic gates that allow for parallel input to the shift register, and a multiplexer for switching inputs of the shift register. The m

A scrambler includes a linear shift register having logic suitable for generating a scrambling sequence according to a predetermined generator sequence, a plurality of logic gates that allow for parallel input to the shift register, and a multiplexer for switching inputs of the shift register. The multiplexer switches inputs so that the shift register can be loaded with a predetermined initial value, and shifted a single bit or shifted a predetermined number of bits though the generator sequence.

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1. A scrambler for generating a scrambling sequence, the scrambler comprising:an X-tap linear feedback shift register having X registers arranged in a linear series for outputting the scrambling sequence according to a predetermined generator sequence;a multiplexer having outputs connected to the re

1. A scrambler for generating a scrambling sequence, the scrambler comprising:an X-tap linear feedback shift register having X registers arranged in a linear series for outputting the scrambling sequence according to a predetermined generator sequence;a multiplexer having outputs connected to the registers of the X-tap linear feedback shift register, the multiplexer further having a first set of inputs, a second set of inputs, and a third set of inputs, the third set of inputs being connected to outputs of registers of the X-tap linear feedback shift register for performing a single step shift operation of the X-tap linear feedback register; anda plurality of logic gates connected to the second set of inputs of the multiplexer and to outputs of the registers for performing an n-step shift operation of the X-tap linear feedback register;wherein the sets of inputs correspond to states of selection ends of the multiplexer; and the selection ends of the multiplexer are capable of being set to select the first set of inputs to load the registers of the X-tap linear feedback shift register with a predetermined state, select the second set of inputs to perform the n-step shift operation of the X-tap linear feedback shift register, and select the third set of inputs to perform the single shift operation of the X-tap linear feedback shift register. 2. The scrambler of claim 1 further comprising a counter connected to the selection ends of the multiplexer for setting the states of the selection ends for a predetermined number of clock pluses. 3. The scrambler of claim 1 wherein the plurality of logic gates are XOR gates. 4. The scrambler of claim 1 wherein the X-tap linear feedback shift register is a 17-tap linear feedback shift register having 17 registers, wherein input of a first register comprises output of a fourteenth register XORed with output of a seventeenth register so that the predetermined generator sequence is h(D)=D 17 +D 14 +1. 5. The scrambler of claim 4 wherein the n-step shift operation is a 24-bit shift operation. 6. The scrambler of claim 5 as part of a device operating in a forward packet data channel (F-PDCH) of a code division multiple access specification (cdma2000) for third generation (3G wireless communication systems. 7. A scrambler for generating a scrambling sequence, the scrambler comprising:a series of registers, each register having an input and an output;a series of multiplexing means, each multiplexing means for selecting one of a first input, a second input and a third input, and to provide the selected input to a corresponding register; wherein each first input is connected to an initial value input to perform an initial value loading operation, and each third input is fed from the output of a previous register to perform a single step shift operation;a series of paralleling XOR means for performing an n-step shift operation, each paralleling XOR means having an output connected to the second input of a corresponding multiplexing means; anda tap XOR means with output connected to the third input of the multiplexing means corresponding to a first register for performing the single step shift operation;wherein inputs to the series of paralleling XOR means and the tap XOR means are outputs of the series of registers arranged such that the series of registers form a series-parallel linear feedback shift register; and the series of multiplexing means is capable of being set so that the series-parallel linear feedback shift register is capable of performing the single step shift operation, performing the n-step shift operation, or performing the initial value loading operation. 8. The scrambler of claim 7 further wherein the series of registers comprises 17 registers, the series of multiplexing means comprises 17 multiplexers each capable of at least three-to-one selection functionality, and the series of paralleling XOR means comprises 17 XOR gates. 9. The scrambler of claim 8 wherein inputs to the series of paralleling XOR gates and the tap XOR gate are outputs of the series of registers arranged such that the series-parallel linear feedback shift register is a 17-tap linear feedback shift register consistent with a generator sequence of h(D)=D 17 +D 14 +1. 10. The scrambler of claim 9 wherein the n-bit shift operation is a shift of 24 bits consistent with a 17-tap linear feedback shift register. 11. The scrambler of claim 10 further comprising a counter for setting the multiplexing means for a predetermined number of clock pluses for performing a succession of 24-bit shift operations. 12. The scrambler of claim 10 as part of a device operating in a forward packet data channel (F-PDCH) of a code division multiple access specification (cdma2000) for third generation (3G) wireless communication systems. 13. A method for generating a scrambling sequence, the method comprising:providing a series-parallel linear feedback shift register capable of performing a single step shift operation, performing an n-step shift operation, and being loaded with initial values;loading the series-parallel linear feedback shift register with initial values;performing a predetermined number of n-step shift operations with the series-parallel linear feedback shift register; andperforming a predetermined number of single step shift operations with the series-parallel linear feedback shift register. 14. The method of claim 13 further comprising outputting contents of the series-parallel linear feedback shift register while performing at least a portion of the predetermined number of the single step shift operations, said output being the scrambling sequence. 15. The method of claim 13 wherein performing the predetermined number of n-step shift operations is according to output of a counter. 16. The method of claim 13 wherein the series-parallel linear feedback shift register is a 17-tap linear feedback shift register having a generator sequence of h(D)=D 17 +D 14 +1, the n-step shift operations are 24-bit shift operations, and the predetermined number of n-step shift operations is between 3 and 324. 17. A device for performing the method of claim 13.