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A method of forming a FINFET CMOS device structure featuring an N channel device and a P channel device formed in the same SOI layer, has been developed. The method features formation of two parallel SOI fin type structures, followed by gate insulator growth on the sides of the SOI fin type structur

A method of forming a FINFET CMOS device structure featuring an N channel device and a P channel device formed in the same SOI layer, has been developed. The method features formation of two parallel SOI fin type structures, followed by gate insulator growth on the sides of the SOI fin type structures, and definition of a conductive gate structure formed traversing the SOI fin type structures while interfacing the gate insulator layer. A doped insulator layer of a first conductivity type is formed on the exposed top surfaces of a first SOI fin type shape, while a second doped insulator layer of a second conductivity type is formed on the exposed top surfaces of the second SOI fin type shape. An anneal procedure results creation of a source/drain region of a first conductivity type in portions of the first SOI fin type shape underlying the first doped insulator layer, and creation of a source/drain region of a second conductivity type in portions of the second SOI fin type shape underlying the second doped insulator layer. Selective deposition of tungsten on exposed top surface of the source/drain regions is then employed to decrease source/drain resistance.

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1. A method of forming a complimentary metal oxide semiconductor (CMOS), device in a silicon on insulator (SOI), layer, comprising the steps of:forming said SOI layer on a semiconductor substrate;forming an insulator layer on said SOI layer;defining a first fin type structure in said insulator layer

1. A method of forming a complimentary metal oxide semiconductor (CMOS), device in a silicon on insulator (SOI), layer, comprising the steps of:forming said SOI layer on a semiconductor substrate;forming an insulator layer on said SOI layer;defining a first fin type structure in said insulator layer and in said SOI layer, andforming a second fin type structure in said insulator layer and in said SOI layer;growing a gate insulator layer on sides of said first fin type structure and on the sides of said second fin type structure;forming a gate structure traversing, and normal in direction to, fin type structures;forming an insulator spacer on sides of portions of said fin type structures not covered by said gate structure, and on sides of said gate structure;forming a first doped insulator layer overlying a first SOI shape, and forming a second doped insulator layer overlying a second SOI shape;performing an anneal procedure to create a first source/drain region of a first conductivity type in said first SOI shape, and to create a second source/drain region of a second conductivity shape in said second SOI shape;removing said first doped insulator layer and said second doped insulator layer; andforming metal shapes on said first source/drain region and on said second source/drain region, resulting in said CMOS device comprised of a first metal oxide semiconductor (MOS), device of a first channel type, featuring said first source/drain region, and comprised of a second MOS device of a second channel type, featuring said second source/drain region. 2. The method of claim 1, wherein said SOI layer is formed at a thickness between about 50 to 5000 Angstroms. 3. The method of claim 1, wherein said insulator layer is a silicon oxide layer obtained at a thickness between about 50 to 5000 Angstroms via LPCVD or PECVD procedures. 4. The method of claim 1, wherein the width of said first fin type structure, and of said second fin type structure, is between about 50 to 1000 Angstroms. 5. The method of claim 1, wherein said gate insulator layer is a silicon dioxide layer, obtained at a thickness between about 10 to 100 Angstroms via a thermal oxidation procedure performed at a temperature between about 700 to 1000° C., in an oxygen-steam ambient. 6. The method of claim 1, wherein said gate structure is defined from a conductive layer chosen from a group containing doped polysilicon, aluminum, aluminum-copper, tungsten, tantalum, tungsten silicide, tantalum silicide, nickel silicide, cobalt silicide, or titanium silicide. 7. The method of claim 1, wherein the thickness of said gate structure is between about 100 to 3000 Angstroms. 8. The method of claim 1, wherein said insulator spacer is a silicon nitride spacer, formed at a thickness between about 300 to 5000 Angstroms. 9. The method of claim 1, wherein said first doped insulator layer is a borosilicate glass (BSG), layer, obtained via LPCVD or PECVD procedures at a thickness between about 100 to 2000 Angstroms, with a B 2 O 3 weight percent between about 3 to 10%. 10. The method of claim 1, wherein said second doped insulator layer is a phosphosilicate glass (PSG), layer, obtained via LPCVD or PECVD procedures at a thickness between about 100 to 2000 Angstroms, with a P 2 O 5 weight percent between about 3 to 10%. 11. The method of claim 1, wherein said anneal procedure is performed in a conventional furnace, or via a rapid thermal anneal procedure, at a temperature between about 700 to 1000° C., for a time between about 1 to 60 min. 12. The method of claim 1, wherein said first doped insulator layer and said second doped insulator layer are removed using a buffered hydrofluoric acid solution. 13. The method of claim 1, wherein said metal shapes formed on said first source/drain region and on said second source/drain region, are comprised of tungsten. 14. The method of claim 1, wherein said metal shapes are tungsten metal shapes, obtained at a thickness between about 100 to 3000 Angstroms, via selective chemical vapor deposition procedures performed at a temperature between about 500 to 1000° C., using tungsten hexafluoride as a source. 15. A method of forming a FINFET CMOS device in a silicon on insulator (SOI), layer, comprising the steps of:forming said SOI layer on a semiconductor substrate;depositing a silicon oxide layer on said SOI layer;performing a first anisotropic reactive ion etch (RIE) procedure to define a first fin type structure in said silicon oxide layer and in said SOI layer, and to define a second fin type structure in said silicon oxide layer and in said SOI layer, with said second fin type structure parallel in direction with said first fin type structure;growing a silicon dioxide gate insulator layer on sides of fin type structures;depositing a conductive layer;performing a second anisotropic RIE procedure to form a conductive gate structure traversing, and normal in direction to, said fin type structures;depositing a silicon nitride layer;performing a third anisotropic RIE procedure to form a silicon nitride spacer on sides of the portions of said fin type structures not covered by said conductive gate structure, and on sides of said conductive gate structure;removing said silicon oxide layer from portions of said fin type structures not covered by said conductive gate structure, exposing a first SOI shape of said first fin type structure, and exposing a second SOI shape of said second fin type structure;depositing a first doped insulator layer;removing said first doped insulator layer from a region overlying said second fin type structure;depositing a second doped insulator layer directly overlying said second fin type structure, while said second doped insulator layer overlays said first doped insulator layer in a region in which said first doped insulator layer directly overlays said first fin type structure;performing an anneal procedure to create a first source/drain region, of a first conductivity type, in said first SOI shape of said first fin type structure, and to create a second source/drain region, of a second conductivity type, in said second SOT shape of said second fin type structure;removing said first doped insulator layer and said second doped insulator layer; andselectively depositing tungsten on source/drain regions resulting in said FINFET CMOS device, featuring a first metal oxide semiconductor (MOS), device of a first channel type, comprised with said first source/drain region, and featuring a second MOS device of a second channel type, comprised with said second source/drain region. 16. The method of claim 15, wherein said SOI layer is formed at a thickness between about 50 to 5000 Angstroms. 17. The method of claim 15, wherein said silicon oxide layer is obtained at a thickness between about 50 to 5000 Angstroms via LPCVD or PECVD procedures. 18. The method of claim 15, wherein the width of said first fin structure and of said second fin structure is between about 50 to 1000 Angstroms. 19. The method of claim 15, wherein said silicon dioxide gate insulator layer is obtained at a thickness between about 10 to 100 Angstroms via a thermal oxidation procedure performed at a temperature between about 700 to 1000° C., in an oxygen-steam ambient. 20. The method of claim 15, wherein said conductive layer, used for said conductive gate structure, is chosen from a group containing doped polysilicon, aluminum, aluminum-copper, tungsten, tantalum, tungsten silicide, tantalum silicide, nickel silicide, cobalt silicide, or titanium silicide. 21. The method of claim 15, wherein said silicon nitride spacer is formed at a thickness between about 300 to 5000 Angstroms. 22. The method of claim 15, wherein said first doped insulator layer is a borosilicate glass (BSG), layer, obtained via LPCVD or PECVD procedures, at a thickness between about 100 to 2000 Angstroms, with a B 2 O 3 weight percent between about 3 to 10%. 23. The method of claim 15, wherein s aid second doped insulator layer is a phosphosilicate glass (PSG), layer, obtained via LPCVD or PECVD procedures, at a thickness between about 100 to 2000 Angstroms, with a P 2 O 5 weight percent between about 3 to 10%. 24. The method of claim 15, wherein said anneal procedure is performed in a conventional furnace, or via a rapid thermal anneal procedure, at a temperature between about 700 to 1000° C., for a time between about 1 to 60 min. 25. The method of claim 15, wherein said first doped insulator layer and said second doped insulator layer are removed using a buffered hydrofluoric acid solution. 26. The method of claim 15, wherein said tungsten layer is selectively deposited to a thickness between about 100 to 3000 Angstroms, via selective chemical vapor deposition procedures, performed at a temperature between about 500 to 1000° C., using tungsten hexafluoride as a source.