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In a telecommunication system where data frames of a plurality of channels (CH 1 ,CH 2 . . . CHn) arrive with respective different time-offsets with respect to a common synchronization clock (WR, R/W, RD, T) of an internal frame structure of a decoder (DEC), three frame memories (RAM 1 , RAM 2 , RAM

In a telecommunication system where data frames of a plurality of channels (CH 1 ,CH 2 . . . CHn) arrive with respective different time-offsets with respect to a common synchronization clock (WR, R/W, RD, T) of an internal frame structure of a decoder (DEC), three frame memories (RAM 1 , RAM 2 , RAM 3 ) are used for performing a time-alignment of the data frames. The data frames are respectively written to two frame memories (RAM 1 , RAM 2 ) having a read state and a reading of one frame memory (RAM 3 ) is performed beginning with the occurrence of the common synchronization clock (T). A cyclic switching of the read/write state of the frame memories (RAM 1 , RAM 2 , RAM 3 ) is performed, such that always two frame memories (RAM 1 , RAM 2 ) are in a write-state (WR) and one frame memory (RAM 3 ) is in a read-state (RD) The frame memory (RAM 3 ) in the read-state is read out synchronized to the common synchronization clock.

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1. A time-alignment apparatus of a receiver of a telecommunication system for receiving successive data frames on a plurality of channels, wherein said respective data frames on said channels are not time-aligned, and for outputting said data frames of all channels time-aligned to a common synchroni

1. A time-alignment apparatus of a receiver of a telecommunication system for receiving successive data frames on a plurality of channels, wherein said respective data frames on said channels are not time-aligned, and for outputting said data frames of all channels time-aligned to a common synchronisation clock, comprising:a) at least a first, second and third read/write frame memory for respectively storing one data frame of each of said channels, said frame memories each having a write state in which data is written to said frame memories by an input means and a read state in which data is read from said frame memories by an output means; andb) a control unit for cyclically switching said three frame memories through a first to third alignment mode synchronized to said common synchronisation clock such thatb1) in said first alignment mode said first and second frame memory are in a write state and said third frame memory is in a read state;b2) in said second alignment mode said second and third frame memory are in a write state and said first frame memory is in a read state;b3) in said third alignment mode said third and first frame memory are in a write state and said second frame memory is in a read state;b4) wherein after each mode switching a newly arriving data frame of any channel is always written to a frame memory which was in a read state in the previous mode; andb5) wherein data frames are always read from the frame memory having a read state time-aligned to said common synchronization clock. 2. A time-alignment apparatus according to claim 1, wherein each frame memory comprises a plurality of matrices respectively associated with a respective channel, said matrices consisting of a predetermined number of columns and rows according to the desired interleaving depth for storing one respective data frame, wherein said input means writes one data frame for each channel into an associated matrix of a frame memory having a write state in the row direction, and wherein a de-interleaving means reads out data from matrices of a frame memory in a read state columnwise time-aligned with each common synchronisation clock. 3. A time-alignment apparatus according to claim 2, wherein said data of said data frames is data from a demodulator/equalizer composed of soft-decision symbols, wherein said soft-decision symbols are stored in memory cells of matrices of said frame memories. 4. A receiver of a telecommunication system comprising one or more time-alignment apparatus according to claim 1. 5. A receiver according to claim 4,wherein said receiver is a CDMA-receiver. 6. A telecommunication system comprising one or more receivers according to claim 4. 7. A telecommunication system according to claim 6,wherein said telecommunication system performs communications using a CDMA technique. 8. A telecommunication system according to claim 6,whereina transmitter codes said data of said data frames according to a convolutional coding technique, wherein said coded data is stored soft-symbolwise in said frame memories in said receivers. 9. A method for time-alignment of successive data frames on a plurality of channels, wherein said respective data frames on said channels are not time-aligned, and for outputting said data frames of all channels time-aligned to a common synchronisation clock, comprising the following steps:a) writing data frames into at least a first, second and third read/write frame memory for respectively storing one data frame of each of said channels, said frame memories each having a write state in which data is written to said frame memories and a read state in which data frames is read from said frame memories; andb) cyclically switching said three frame memories through a first to third alignment mode synchronized to said common synchronisation clock, whereinb1) in said first alignment mode data frames are written to said first and second frame memory in a write state and data frames are read from said third fram e memory in a read state starting with each common synchronization clock;b2) in said second alignment mode data frames are written to said second and third frame memory in a write state and data frames are read from said first frame memory in a read state starting with each common synchronization clock;b3) in said third alignment mode data frames are written to said third and first frame memory in a write state and data frames are read from said second frame memory in a read state starting with each common synchronization clock; whereinb4) after each mode switching a newly arriving data frame of any channel is always written to a frame memory which was in a read state in the previous mode;b5) wherein data frames are always read from the frame memory having a read state time-aligned to said common synchronization clock. 10. A method according to claim 9,wherein each frame memory comprises a plurality of matrices respectively associated with a respective channel, said matrices consisting of a predetermined number of columns and rows according to the desired interleaving depth for storing one respective data frame, wherein one data frame for each channel is written into an associated matrix of a frame memory having a write state in the row direction, and wherein data from matrices of a frame memory in a read state is read out columnwise time-aligned with each common synchronisation clocks. 11. A method according to claim 9,wherein said data of said data frames is data from a demodulator/equalizer composed of soft decision symbols, wherein said soft-decision symbols are stored in memory cells of matrices of said memories. 12. A time alignment apparatus of a receiver of a telecommunication system for receiving successive data frames on a plurality of channels, wherein said respective data frames on said channels are not time-aligned, and for outputting said data frames of all channels time-aligned to a common synchronisation clock, comprising:a) at least a first, second and third read/write frame memory for respectively storing one data frame of each of said channels, said frame memories each having a write state in which data is written to said frame memories by an input means and a read state in which data is read from said frame memories by an output means; andb) a control unit for cyclically switching said three frame memories through a first to third alignment mode synchronized to said common synchronisation clock such thatb1) in said first alignment mode said first and second frame memory are in a write state and said third frame memory is in a read state;b2) in said second alignment mode said second and third frame memory are in a write state and said first frame memory is in a read state;b3) in said third alignment mode said third and first frame memory are in a write state and said second frame memory is in a read state;b4) wherein after each mode switching a newly arriving data frame of any channel is always written to a frame memory which was in a read state in the previous mode; andb5) wherein data frames are always read from the frame memory having a read state time-aligned to said common synchronization clock; and whereinc) each frame memory comprises a plurality of matrices respectively associated with a respective channel, said matrices consisting of a predetermined number of columns and rows according to the desired interleaving depth for storing one respective data frame, wherein said input means writes one data frame for each channel into an associated matrix of a frame memory having a write state in the row direction, and wherein a de-interleaving means reads out data from matrices of a frame memory in a read state columnwise time-aligned with each common synchronisation clock. 13. A time alignment apparatus of a receiver of a telecommunication system for receiving successive data frames on a plurality of channels, wherein said respective data frames on said channels are not time-aligned, and for outputting said data frames of all channels time-aligned to a common synchronisation clock, comprising:a) at least a first, second and third read/write frame memory for respectively storing one data frame of each of said channels, said frame memories each having a write state in which data is written to said frame memories by an input means and a read state in which data is read from said frame memories by an output means; andb) a control unit for cyclically switching said three frame memories through a first to third alignment mode synchronized to said common synchronization clock such thatb1) in said first alignment mode said first and second frame memory are in a write state and said third frame memory is in a read state;b2) in said second alignment mode said second and third frame memory are in a write state and said first frame memory is in a read state;b3) in said third alignment mode said third and first frame memory are in a write state and said second frame memory is in a read state;b4) wherein after each mode switching a newly arriving data frame of any channel is always written to a frame memory which was in a read state in the previous mode; andb5) wherein data frames are always read from the frame memory having a read state time-aligned to said common synchronization clock; and whereinc) each frame memory comprises a plurality of matrices respectively associated with a respective channel, said matrices consisting of a predetermined number of columns and rows according to the desired interleaving depth for storing one respective data frame, wherein said input means writes one data frame for each channel into an associated matrix of a frame memory having a write state in the row direction, and wherein a de-interleaving means reads out data from matrices of a frame memory in a read state columnwise time-aligned with each common synchronisation clock; andd) said data of said data frames is data from a demodulator/equalizer composed of soft-decision symbols, wherein said soft-decision symbols are stored in memory cells of matrices of said frame memories. 14. A method for time-alignment of successive data frames on a plurality of channels, wherein said respective data frames on said channels are not time-aligned, and for outputting said data frames of all channels time-aligned to a common synchronisation clock, comprising the following steps;a) writing data frames into at least a first, second and third read/write frame memory for respectively storing one data frame of each of said channels, said frame memories each having a write state in which data is written to said frame memories and a read state in which data frames is read from said frame memories; andb) cyclically switching said three frame memories through a first to third alignment mode synchronized to said common synchronisation clock, whereinb1) in said first alignment mode data frames are written to said first and second frame memory in a write state and data frames are read from said third frame memory in a read state starting with each common synchronization clock;b2) in said second alignment mode data frames are written to said second and third frame memory in a write state and data frames are read from said first frame memory in a read state starting with each common synchronization clock;b3) in said third alignment mode data frames are written to said third and first frame memory in a write state and data frames are read from said second frame memory in a read state starting with each common synchronization clock; whereinb4) after each mode switching a newly arriving data frame of any channel is always written to a frame memory which was in a read state in the previous mode;b5) wherein data frames are always read from the frame memory having a read state time-aligned to said common synchronization clock; and whereinc) each frame memory comprises a plurality of matrices respectively associated with a respective channel, said matrices consisting of a predetermined numbe r of columns and rows according to the desired interleaving depth for storing one respective data frame, wherein one data frame for each channel is written into an associated matrix of a frame memory having a write state in the row direction, and wherein data from matrices of a frame memory in a read state is read out columnwise time-aligned with each common synchronisation clock. 15. A method for time-alignment of successive data frames on a plurality of channels, wherein said respective data frames on said channels are not time-aligned, and for outputting said data frames of all channels time-aligned to a common synchronisation clock, comprising the following steps:a) writing data frames into at least a first, second and third read/write frame memory for respectively storing one data frame of each of said channels, said frame memories each having a write state in which data is written to said frame memories and a read state in which data frames is read from said frame memories; andb) cyclically switching said three frame memories through a first to third alignment mode synchronized to said common synchronisation clock, whereinb1) in said first alignment mode data frames are written to said first and second frame memory in a write state and data frames are read from said third frame memory in a read state starting with each common synchronization clock;b2) in said second alignment mode data frames are written to said second and third frame memory in a write state and data frames are read from said first frame memory in a read state starting with each common synchronization clock;b3) in said third alignment mode data frames are written to said third and first frame memory in a write state and data frames are read from said second frame memory in a read state starting with each common synchronization clock; whereinb4) after each mode switching a newly arriving data frame of any channel is always written to a frame memory which was in a read state in the previous mode;b5) wherein data frames are always read from the frame memory having a read state time-aligned to said common synchronization clock; and whereinc) each frame memory comprises a plurality of matrices respectively associated with a respective channel, said matrices consisting of a predetermined number of columns and rows according to the desired interleaving depth for storing one respective data frame, wherein one data frame for each channel is written into an associated matrix of a frame memory having a write state in the row direction, and wherein data from matrices of a frame memory in a read state is read out columnwise time-aligned with each common synchronisation clock; and whereind) said data of said data frames is data from a demodulator/equalizer composed of soft decision symbols, wherein said soft-decision symbols are stored in memory cells of matrices of said memories.