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A semiconductor device includes an insulating layer, a semiconductor board formed on a selected portion of the insulating layer, a semiconductor layer formed on at least one of the major side surfaces of the semiconductor board, which is different from the semiconductor board in lattice constant, an

A semiconductor device includes an insulating layer, a semiconductor board formed on a selected portion of the insulating layer, a semiconductor layer formed on at least one of the major side surfaces of the semiconductor board, which is different from the semiconductor board in lattice constant, and having source and drain regions and a channel region therebetween, the area of the channel region being larger than that of the bottom surface of the semiconductor board, which contacts the insulating layer, and a gate electrode formed on the channel region via a gate insulating layer.

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1. A semiconductor device comprising:an insulating layer having a major surface;a semiconductor board formed on a selected portion of the major surface of the insulating layer, the semiconductor board having a bottom surface in contact with the major surface of the insulating layer, at least two pla

1. A semiconductor device comprising:an insulating layer having a major surface;a semiconductor board formed on a selected portion of the major surface of the insulating layer, the semiconductor board having a bottom surface in contact with the major surface of the insulating layer, at least two planar major side surfaces in parallel to each other, and substantially perpendicular to the major surface of the insulating layer, and an upper surface opposed to the bottom surface;a semiconductor layer formed on at least one of the major side surfaces of the semiconductor board, the semiconductor layer having a lattice constant different from that of the semiconductor board, and having source and drain regions spaced apart from each other and a channel region between the source and drain regions, a channel length direction of the channel region being substantially parallel to the major surface of the insulating layer, and an area of the surface of the channel region being larger than the area of the bottom surface of the semiconductor board;a gate insulating layer formed on the channel region of the semiconductor layer; anda gate electrode formed on the gate insulating layer. 2. The device according to claim 1, wherein the semiconductor board is a SiGe board and the semiconductor layer is a strained Si layer. 3. The device according to claim 1, wherein the semiconductor board is a Si board and the semiconductor layer is a strained SiGe layer. 4. The device according to claim 1, further comprising:a bipolar transistor formed on the major surface of the insulating layer, and spaced apart from the selected portion where the semiconductor board is formed. 5. The device according to claim 4, wherein the semiconductor board, emitter and collector regions of the bipolar transistor are made of Si, a base region of the bipolar transistor is made of SiGe, and the semiconductor layer is a strained SiGe layer. 6. The device according to claim 4, wherein the semiconductor board and a base region of the bipolar transistor are made of SiGe, an emitter region of the bipolar transistor is made of Si, and the semiconductor layer is a strained Si layer. 7. The device according to claim 1, further comprising a semiconductor substrate which supports the insulating layer. 8. A manufacturing method of the semiconductor device according to claim 1, comprising:forming a multilayered structure of an insulating layer and a SiGe layer;oxidizing the multilayered structure to increase a Ge composition in the SiGe layer;etching the SiGe layer to form on the insulating layer a SiGe board having a bottom surface in contact with the insulating layer, at least two planar major side surfaces in parallel to each other and substantially perpendicular to a surface of the insulating layer, and an upper surface opposed to the bottom surface;forming a Si layer on at least one of the major side surfaces of the SiGe layer;forming a source region, a drain region, and a gate insulating layer on the Si layer, andforming a gate electrode on the gate insulating layer between the source and drain regions. 9. A semiconductor device comprising:an insulating layer having a major surface;a p-type semiconductor board formed on a first selected portion of the major surface of the insulating layer, the p-type semiconductor board having a bottom surface in contact with the major surface of the insulating layer, at least two planar major side surfaces in parallel to each other, and substantially perpendicular to the major surface of the insulating layer, and an upper surface opposed to the bottom surface of the p-type semiconductor board;a first semiconductor layer formed on at least one of the major side surfaces of the p-type semiconductor board, the first semiconductor layer having a lattice constant different from that of the p-type semiconductor board and having n-type source and drain regions spaced apart from each other and a first channel region provided in a p-type region between the n-type source and drain regions, a channel length direction of the first channel region being substantially parallel to the major surface of the insulating layer, and an area of the surface of the first channel region being larger than the area of the bottom surface of the p-type semiconductor board;a first gate insulating layer formed on the first channel region of the first semiconductor layer;a first gate electrode formed on the first gate insulating layer;an n-type semiconductor board formed on a second selected portion of the major surface of the insulating layer, the n-type semiconductor board having a bottom surface in contact with the major surface of the insulating layer, at least two planar major side surfaces in parallel to each other, and substantially perpendicular to the major surface of the insulating layer, and an upper surface opposed to the bottom surface of the n-type semiconductor board;a second semiconductor layer formed on at least one of the major side surfaces of the n-type semiconductor board, the second semiconductor layer having a lattice constant different from that of the n-type semiconductor board and having p-type source and drain regions spaced apart from each other and a second channel region provided in an n-type region between the p-type source and drain regions, a channel length direction of the second channel region being substantially parallel to the major surface of the insulating layer, and an area of the surface of the second channel region being larger than the area of the bottom surface of the n-type semiconductor board;a second gate insulating layer formed on the second channel region of the second semiconductor layer; anda second gate electrode formed on the second gate insulating layer. 10. The device according to claim 9, wherein the first channel region is formed in a (100) or equivalent plane of the first semiconductor layer, and the second channel region is formed in a (110) or equivalent plane of the second semiconductor layer. 11. The device according to claim 9, wherein the p-type semiconductor board is a p-type SiGe board, the first semiconductor layer is a strained Si layer, the n-type semiconductor board is an n-type SiGe board, and the second semiconductor layer is a strained Si layer. 12. The device according to claim 9, wherein the p-type semiconductor board is a p-type SiGe board, the first semiconductor layer is a strained Si layer, the n-type semiconductor board is an n-type Si board, and the second semiconductor layer is a strained SiGe layer. 13. The device according to claim 9, further comprising:a bipolar transistor formed on the major surface of the insulating layer, and spaced apart from the first selected portion where the p-type semiconductor board is formed. 14. The device according to claim 13, wherein the p-type semiconductor board, and emitter and collector regions of the bipolar transistor are made of Si, a base region of the bipolar transistor is made of SiGe, and the first semiconductor layer is a strained SiGe layer. 15. The device according to claim 13, wherein the p-type semiconductor board is a SiGe board, the first semiconductor layer is a strained Si layer, the n-type semiconductor board is a Si board, the second semiconductor layer is a strained SiGe layer, emitter and collector regions of the bipolar transistor are formed in a Si layer, and the base region of the bipolar transistor are made of SiGe. 16. The device according to claim 9, further comprising a semiconductor substrate which supports the insulating layer. 17. A semiconductor device comprising:an insulating layer having a major surface;a first semiconductor board formed on a first selected portion of the major surface of the insulating layer, the first semiconductor board having a bottom surface in contact with the major surface of the insulating layer, at least two planar major side surfaces in parallel to each other and substantially perpendicular to the major surface of the fi rst insulating layers, and an upper surface opposed to the bottom surface of the first semiconductor board;a first semiconductor layer formed on at least one of the major side surfaces of the first semiconductor board, the first semiconductor layer having a lattice constant different from that of the first semiconductor board, and having a first source region and a first drain region spaced apart from each other and a first channel region provided between the first source region and the first drain region, a channel length direction of the first channel region being substantially parallel to the major surface of the insulating layer, and an area of the surface of the first channel region being larger than the area of the bottom surface of the first semiconductor board;a first gate insulating layer formed on the first channel region of the first semiconductor layer;a first gate electrode formed on the first gate insulating layer;a second semiconductor board formed on a second selected portion of the major surface of the insulating layer, the second semiconductor board having a bottom surface in contact with the major surface of the insulating layer, at least two planar major side surfaces in parallel to each other and substantially perpendicular to the major surface of the second insulating layers, and an upper surface opposed to the bottom surface of the second semiconductor board;a second semiconductor layer formed on at least one of the major side surfaces of the second semiconductor board, the second semiconductor layer having a lattice constant different from that of the second semiconductor board, and having a second source region and a second drain region spaced apart from each other and a second channel region provided between the second source region and the second drain region, a channel length direction of the second channel region being substantially parallel to the major surface of the insulating layer, and an area of the surface of the second channel region being larger than the area of the bottom surface of the second semiconductor board;a second gate insulating layer formed on the second channel region of the second semiconductor layer;a second gate electrode formed on the second gate insulating layer. 18. The device according to claim 17, wherein the first and second semiconductor boards are SiGe boards, and the first and second semiconductor layers are Si layers. 19. The device according to claim 17, wherein the first and second semiconductor boards are Si boards, and the first and second semiconductor layers are strained SiGe layers. 20. The device according to claim 17, further comprising a semiconductor substrate which supports the insulating layer.