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Fabrication of memory cell capacitors in an over/under configuration facilitates increased capacitance values for a given die area. A pair of memory cells sharing a bit-line contact include a first capacitor below the substrate surface. The pair of memory cells further include a second capacitor suc

Fabrication of memory cell capacitors in an over/under configuration facilitates increased capacitance values for a given die area. A pair of memory cells sharing a bit-line contact include a first capacitor below the substrate surface. The pair of memory cells further include a second capacitor such that at least a portion of the second capacitor is underlying the first capacitor. Such memory cell capacitors can thus have increased surface area for a given capacitor height versus memory cell capacitors formed strictly laterally adjacent one another. The memory cell capacitors can be fabricated using silicon-on-insulator (SOI) techniques. The memory cell capacitors are useful for a variety of memory arrays, memory devices and electronic systems.

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1. A memory cell, comprising:an access transistor having a first source/drain region and a second source/drain region, wherein the second source/drain region is coupled to a bit line; anda capacitor below a channel region of the access transistor, wherein the capacitor is coupled to the first source

1. A memory cell, comprising:an access transistor having a first source/drain region and a second source/drain region, wherein the second source/drain region is coupled to a bit line; anda capacitor below a channel region of the access transistor, wherein the capacitor is coupled to the first source/drain region of the access transistor;wherein the capacitor is overlying at least a portion of a capacitor of a second memory cell; andwherein the second memory cell has an access transistor having a source/drain region coupled to the bit line. 2. The memory cell of claim 1, wherein the first source/drain region and the second source/drain region are formed in an epitaxial silicon layer. 3. A memory cell, comprising:an access transistor having a first source/drain region and a second source/drain region, wherein the second source/drain region is coupled to a bit line; anda capacitor coupled to the first source/drain region of the access transistor through an extension;wherein the extension is laterally adjacent a second capacitor of a second memory cell; andwherein the capacitor of the memory cell is underlying at least a portion of the second capacitor of the second memory cell. 4. The memory cell of claim 3, wherein the extension is a portion of a storage node of the capacitor. 5. The memory cell of claim 4, wherein the extension comprises a conductively-doped polysilicon. 6. The memory cell of claim 5, wherein the entire storage node of the capacitor comprises conductively-doped polysilicon. 7. A memory device, comprising:a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the memory device, and a gate coupled to a first word line of the memory device;a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the memory device, wherein the second word line is different from the first word line;wherein the first memory cell further includes a cell capacitor coupled to the first source/drain region of the first access transistor through an extension; andwherein the second memory cell further includes a cell capacitor interposed between the second access transistor and the cell capacitor of the first memory cell. 8. The memory device of claim 7, wherein the cell capacitor of the first memory cell and the cell capacitor of the second memory cell each share surface area of a die containing the memory device. 9. A memory device, comprising:a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the memory device, and a gate coupled to a first word line of the memory device;a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the memory device, wherein the second word line is different from the first word line;wherein a cell capacitor of the first memory cell is underlying the first source/drain region of the first memory cell; andwherein the cell capacitor of the first memory cell is overlying at least a portion of a cell capacitor of the second memory cell. 10. A memory device, comprising:a plurality of bit lines;a plurality of word lines;an array of memory cells, wherein the array of memory cells comprises:a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the plurality of bit lines, and a gate coupled to a first word line of the plurality of word lines;a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the plurality of word lines different from the first word line;wherein the first memory cell further includes a cell capacitor coupled to the first source/drain region of the first access transistor through an extension; andwherein the second memory cell further includes a cell capacitor interposed between the second access transistor and the cell capacitor of the first memory cell. 11. The memory device of claim 10, wherein the cell capacitor of the first memory cell and the cell capacitor of the second memory cell are each underlying the second access transistor. 12. A memory device, comprising:a plurality of bit lines;a plurality of word lines;an array of memory cells, wherein the array of memory cells comprises:a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the plurality of bit lines, and a gate coupled to a first word line of the plurality of word lines;a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the plurality of word lines different from the first word line;wherein a cell capacitor of the first memory cell is underlying the first source/drain region of the first memory cell; andwherein the cell capacitor of the first memory cell is overlying at least a portion of a cell capacitor of the second memory cell. 13. The memory device of claim 12, wherein the cell capacitor of the second memory cell is underlying the first source/drain region of the first memory cell. 14. The memory device of claim 12, wherein each cell capacitor is a container capacitor. 15. A memory cell, comprising:an access transistor having a first source/drain region and a second source/drain region, wherein the second source/drain region is coupled to a bit line; anda container capacitor coupled to the first source/drain region of the access transistor;wherein the container capacitor is overlying at least a portion of a container capacitor of a second memory cell; andwherein the second memory cell has an access transistor having a source/drain region coupled to the bit line. 16. The memory cell of claim 15, wherein the source/drain region of the access transistor of the second memory cell that is coupled to the bit line is shared with the second source/drain region of the memory cell. 17. The memory cell of claim 15, wherein the container capacitor of the second memory cell is underlying both the first and second source/drain regions of the access transistor of the memory cell. 18. A memory cell, comprising:an access transistor having a first source/drain region and a second source/drain region, wherein the second source/drain region is coupled to a bit line; anda container capacitor coupled to the first source/drain region of the access transistor through an extension;wherein the extension is laterally adjacent a second container capacitor of a second memory cell; andwherein the container capacitor of the memory cell is underlying at least a portion of the second container capacitor of the second memory cell. 19. A memory device, comprising:a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the memory device, and a gate coupled to a first word line of the memory device;a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the memory device, wherein the second word line is different from the first word line;wherein the first memory cell further includes a first cell capacitor below a channel region of the first access transistor and coupled to the first source/drain region of the first access transistor; andwherein the second memory cell further includes a second cell capac itor at least a portion of which is below the first cell capacitor. 20. The memory device of claim 19, wherein the second cell capacitor is underlying the first and second source/drain regions of the first and second access transistors. 21. A memory device, comprising:a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the memory device, and a gate coupled to a first word line of the memory device;a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the memory device, wherein the second word line is different from the first word line;wherein the first memory cell further includes a cell capacitor below a channel region of the first access transistor and coupled to the first source/drain region of the first access transistor; andwherein the second memory cell further includes a cell capacitor interposed between a channel region of the second access transistor and the cell capacitor of the first memory cell. 22. The memory device of claim 21, wherein the cell capacitor of the first memory cell is also below a channel region of the second access transistor.