초록 ▼

A programmable logic device (PLD) is provided that includes at least one dedicated output routing channel configured to facilitate the processing of output signals generated by multiple function-specific blocks (FSBs). The output routing channel includes a plurality of functional units that may be p

A programmable logic device (PLD) is provided that includes at least one dedicated output routing channel configured to facilitate the processing of output signals generated by multiple function-specific blocks (FSBs). The output routing channel includes a plurality of functional units that may be programmably selectively chained, wherein each functional unit contains an operational block and output selection logic that are configured to programmably selectively implement any of a variety of operations (e.g., bitwise, logical, arithmetic, etc.) that may be performed on the outputs of single FSBs and/or several FSBs. In addition to the output routing channel, the PLD may also contain at least one input routing channel that is configured to facilitate the routing, registering, and/or selection of FSB input signals. In some cases, the FSB input routing channel may also include circuitry for performing elementary processing operations.

대표청구항 ▼

1. A programmable logic device, comprising:a plurality of programmable logic blocks disposed on the device in a two-dimensional array of intersecting rows and columns;a plurality of function-specific blocks (FSBs) arranged in an additional column included within the two-dimensional array, wherein ea

1. A programmable logic device, comprising:a plurality of programmable logic blocks disposed on the device in a two-dimensional array of intersecting rows and columns;a plurality of function-specific blocks (FSBs) arranged in an additional column included within the two-dimensional array, wherein each FSB includes circuitry at least partly hardwired to perform a specific function on at least one multi-bit FSB input signal to generate at least one multi-bit FSB output signal; andan output routing channel extending along the plurality of FSBs, wherein the output routing channel is programmably configurable to perform processing operations on the multi-bit FSB output signals generated by the plurality of FSBs. 2. The device defined in claim 1, wherein the output routing channel is further programmably configurable to concurrently perform a plurality of separate processing operations on the associated multi-bit FSB output signals generated by different subpluralities of FSBs. 3. The device defined in claim 1, wherein the output routing channel includes a plurality of functional units, wherein each functional unit has at least one functional unit input and at least one functional unit output, and is programmably selectively configurable to:receive an associated multi-bit FSB output signal from a respective one of the FSBs in the plurality of FSBs,perform an elementary operation on the associated multi-bit FSB output signal to generate a functional unit output signal, andprovide the functional unit output signal to at least one of a plurality of signal destinations. 4. The device defined in claim 3, wherein the plurality of functional units contained within the output routing channel are serially-aligned and are programmably selectively chainable. 5. The device defined in claim 3, wherein each functional unit contains an operational block that is configured to perform the elementary operation on at least one operational block input signal in generating at least one operational block output signal, wherein the associated multi-bit FSB output signal received by the functional unit is provided to the operational block contained therein as a first operational block input signal. 6. The device defined in claim 5, wherein each functional unit further contains output selection logic, wherein the output selection logic is programmably selectively configurable for operation in a plurality of modes for programmably selectively passing the functional unit output signal to least one of the plurality of signal destinations, whereinin a first mode, the output selection logic is configured to selectively pass the associated multi-bit FSB output signal received by the functional unit as the functional unit output signal, andin a second mode, the output selection logic is configured to selectively pass the operational block output signal as the functional unit output signal. 7. The device defined in claim 6, further comprising general interconnection resources configured to convey signals to, from, and amongst the programmable logic blocks, whereina first signal destination in the plurality of signal destinations is the general interconnection resources, anda second signal destination in the plurality of signal destinations is an associated functional unit input of a neighboring functional unit. 8. The device defined in claim 7, wherein the neighboring functional unit is configured to receive the functional unit output signal as a second operational block input signal to an associated operational block contained within that neighboring functional unit. 9. The device defined in claim 8, wherein the associated elementary operation performed by the associated operational block contained within the neighboring functional unit is a combination function that arithmetically combines its associated first operational block input signal with its associated second operational block input signal. 10. The device defined in claim 1, further comprising:general in terconnection resources configured to convey signals amongst the plurality of programmable logic blocks; andan input routing channel extending along the plurality of FSBs, wherein the input routing channel contains a plurality of input processing blocks, each input processing block being associated with a respective one of the FSBs and being configured to programmably selectively accept at least one signal from the general interconnection resources and to generate at least one multi-bit FSB input signal to be conveyed to an associated FSB. 11. The device defined in claim 10, wherein each input processing block contains registering and selection logic, wherein the registering and selection logic is configured to programmably selectively generate registered multi-bit FSB input signals. 12. The device defined in claim 11, wherein each input processing block further contains processing circuitry configured to perform logic operations on at least one signal accepted from the general interconnection resources to generate at least one multi-bit FSB input signal. 13. The device defined in claim 11, wherein the input routing channel further contains common routing resources that span adjacent to the plurality of input processing blocks, wherein the common routing resources are programmably selectively connectable to the registering and selection logic within each input processing block. 14. A data processing system comprising:processing circuitry;a system memory coupled to the processing circuitry; andthe device defined in claim 1 coupled to the processing circuitry and the system memory. 15. A printed circuit board on which is mounted the device defined in claim 1. 16. The printed circuit board defined in claim 15 further comprising:a board memory mounted on the printed circuit board and coupled to the device; andprocessing circuitry mounted on the printed circuit board and coupled to the device. 17. A programmable logic device, comprising:a plurality of programmable logic blocks disposed on the device in a two-dimensional array of intersecting rows and columns;a plurality of multipliers arranged in an additional column included within the two-dimensional array, wherein each multiplier includes circuitry that is at least partly hardwired to multiply a plurality of multi-bit input signals to generate a multi-bit output signal; andan output routing channel extending along the plurality of multipliers, wherein the output routing channel is programmably configurable to perform processing operations on the multi-bit output signals generated by the plurality of multipliers. 18. The device defined in claim 17, wherein the output routing channel contains a plurality of adders arranged in a programmably selectively-chainable adder chain, wherein each adder is configured to add a first adder input signal to a second adder input signal to generate an adder output signal. 19. The device defined in claim 18, wherein the output routing channel further includes programmable input/output selection circuitry between each pair of adders in the adder chain, wherein the programmable input/output selection circuitry is configured to programmably selectively pass an associated adder output signal of a first adder in the pair to a second adder in the pair as an associated first adder input signal for the second adder. 20. The device defined in claim 19, wherein the programmable input/output selection circuitry between each pair of adders includes register circuitry configured to register the associated adder output signal generated by the first adder, and wherein the programmable input/output selection circuitry is further configured to programmably select between an unregistered and a registered version of the associated adder output signal of the first adder to be conveyed as the associated first adder input signal to the second adder. 21. The device defined in claim 18, wherein the associated multi-bit output signal of each multiplier in the plurality of multipliers is applied as a second adder input signal to a respective one of the adders in the adder chain. 22. The device defined in claim 17, further comprising:general interconnection resources configured to convey signals amongst the plurality of programmable logic blocks; andan input routing channel extending along the plurality of multipliers, wherein the input routing channel contains a plurality of input processing blocks, each input processing block being associated with a respective one of the multipliers and being configured to programmably selectively accept signals from the general interconnection resources and to generate an associated plurality of multi-bit input signals to be conveyed to its associated multiplier. 23. The device defined in claim 22, wherein each input processing block contains registering and selection logic, wherein the registering and selection logic is configured to programmably selectively generate registered multi-bit input signals. 24. The device defined in claim 22, wherein the input routing channel contains a common input bus that spans adjacent to and is programmably selectively connectable to the plurality of input processing blocks, and wherein the common input bus includes registering and selection circuitry configured to programmably selectively convey registered data to each input processing block. 25. The device defined in claim 24, further comprising a feedback conductor configured to convey results from the processing operations performed in the output routing channel to the common input bus. 26. A data processing system comprising:processing circuitry;a system memory coupled to the processing circuitry; andthe device defined in claim 17 coupled to the processing circuitry and the system memory. 27. A printed circuit board on which is mounted the device defined in claim 17. 28. The printed circuit board defined in claim 27 further comprising:a board memory mounted on the printed circuit board and coupled to the device. 29. The printed circuit board defined in claim 27 further comprising:processing circuitry mounted on the printed circuit board and coupled to the device. 30. A programmable logic device, comprising:a plurality of programmable logic blocks disposed on the device in a two-dimensional array of intersecting rows and columns;a plurality of multipliers arranged in an additional column included within the two-dimensional array; andmeans for performing processing operations on output signals generated by the plurality of multipliers, wherein the means for performing the processing operations are included in an output routing channel that extends along the plurality of multipliers. 31. The device defined in claim 30, wherein the output routing channel includes means for selectively adding and registering output signals generated by the plurality of multipliers, wherein the means for selectively adding and registering is programmably selectively configurable for operation in a plurality of modes, wherein in a first mode, the means for selectively adding and registering is programmably selectively configurable to process the output signals as a finite-impulse response filter. 32. The device defined in claim 31, wherein in a second mode, the means for selectively adding and registering is programmably selectively configurable to process the output signals as an adder chain. 33. The device defined in claim 30, further comprising:means for conveying input signals destined for the plurality of multipliers, wherein the means for conveying input signals includes an input routing channel that extends along the plurality of multipliers. 34. A data processing system comprising:processing circuitry;a system memory coupled to the processing circuitry; andthe device defined in claim 30 coupled to the processing circuitry and the system memory. 35. A printed circuit board on which is mounted the device defined in claim 30. 36. The printed circuit board defined in claim 35 further compr ising:a board memory mounted on the printed circuit board coupled to the device. 37. The printed circuit board defined in claim 35 further comprising:processing circuitry mounted on the printed circuit board and coupled to the device.