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A probe board provides signal paths between an integrated circuit (IC) tester and probes accessing terminals on the surfaces of ICs formed on a semiconductor wafer for receiving test signals form the IC tester. A branching signal path within the probe board distributes a test signal produced by one

A probe board provides signal paths between an integrated circuit (IC) tester and probes accessing terminals on the surfaces of ICs formed on a semiconductor wafer for receiving test signals form the IC tester. A branching signal path within the probe board distributes a test signal produced by one channel of the IC tester to several probes. Resistors within the branching signal path resistively isolate the probes from one another so that a fault occurring at any one IC terminal will not affect the logic state of the test signal arriving at any other IC terminal. The isolation resistors are sized relative to signal path characteristic impedances so as to substantially minimize test signal reflections at the branch points.

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1. An apparatus for providing signal paths between an integrated circuit (IC) tester and a plurality of IC terminals so that a driver within the IC tester can concurrently transmit a test signal to the IC terminals, said test signal exhibiting high and low voltage levels representing logic states, w

1. An apparatus for providing signal paths between an integrated circuit (IC) tester and a plurality of IC terminals so that a driver within the IC tester can concurrently transmit a test signal to the IC terminals, said test signal exhibiting high and low voltage levels representing logic states, wherein a fault at any one of the IC terminals conductively linking that IC terminal to a source of potential can drive that IC terminal near either of said high and low voltage levels, the apparatus comprising:a first signal path having a first characteristic impedance for conveying the test signal away from the driver;a plurality of probes, each for conveying the test signal to a separate one of the plurality of IC terminals; anda network comprising resistors for conveying the test signal from the first signal path to each of the probes,wherein the resistors isolate the IC terminals from one another by an amount of resistance that is substantially larger than the first characteristic impedance of the first signal path and sufficiently large to prevent the fault at any one of the IC terminals from affecting a logic state represented by the test signal at any other of the IC terminals. 2. The apparatus in accordance with claim 1 wherein the first signal path and the probes have substantially similar characteristic impedances. 3. The apparatus in accordance with claim 1 wherein the network comprises:a second signal path having a set of taps, the first signal path delivering the test signal to the second signal path, the second signal path conveying the test signal to its taps;a plurality of first resistors, each having a first terminal connected to a separate one of said taps for receiving the test signal, and having a second terminal, each first resistor conveying the test signal from its first terminal to its second terminal; anda plurality of third signal paths, each conveying the test signal from a separate one of the second terminals to a separate one of the probes. 4. The apparatus in accordance with claim 3 wherein the second signal path has a uniform second characteristic impedance between its taps substantially matching the first characteristic impedance of the first signal path. 5. The apparatus in accordance with claim 1 wherein the network comprises:a first node ( 41 ), the first signal path delivering the test signal to the first node;a plurality of second nodes ( 43 );a plurality of second signal paths ( 42 ), each connected for conveying the test signal from the first node to a separate one of the second nodes, and each second signal path having a second characteristic impedance;a plurality of first resistors;a plurality of sets of third signal paths ( 44 ), each set corresponding to a separate one of the second nodes, each third signal path of each set being connected for conveying the test signal from the set's corresponding second node to a separate one of the first resistors, and each third signal path having a third characteristic impedance. 6. The apparatus in accordance with claim 5wherein the second characteristic impedances of the second signal paths are sized relative to the first characteristic impedance of the first signal path so as to substantially minimize test signal reflections at the first node. 7. The apparatus in accordance with claim 6wherein the third characteristic impedances of the third signal paths are sized relative to the second characteristic impedance of the second signal path so as to substantially minimize test signal reflections at the second nodes. 8. The apparatus in accordance with claim 1 wherein the network comprises:a first node ( 66 ), the first signal path delivering the test signal to the first node;a plurality of first resistors ( 67 ), each having a first terminal and a second terminal, the first terminals of all first resistors being connected to the first node such that each resistor conveys the test signal from the first node to its second terminal, anda plurality of secon d signal paths ( 68 ), each linking the second terminal of a separate one of the first resistors to a separate one of the probes. 9. The apparatus in accordance with claim 8 wherein the first resistors are of resistances sized relative to the first characteristic impedance of the first signal path so as to substantially minimize test signal reflections at said first node. 10. The apparatus in accordance with claim 1 wherein the network comprises:a first node ( 82 ), the first signal path delivering the test signal to the first node;a plurality of first resistors, each having a first terminal and a second terminal, the first terminals of all first resistors being connected to the first node such that each first resistor conveys the test signal from the first node to its second terminal,a plurality of second nodes ( 84 , 86 );a plurality of second signal paths, each having a second characteristic impedance and being linked for conveying the test signal from the first node to a separate one of the second nodes;a plurality of sets of second resistors, each set corresponding to a separate one of the second nodes, each second resistor having a third terminal and a fourth terminal, the third terminals of the second resistors of each set being connected to the set's corresponding second node; anda plurality of third signal paths, each third signal path being connected for conveying the test signal from the second terminal of a separate one of the first resistors to a separate one of the probes. 11. The apparatus in accordance with claim 10wherein the first resistors are of resistances sized relative to the first characteristic impedance of the first signal path so as to substantially minimize test signal reflections at the first node. 12. The apparatus in accordance with claim 11 wherein the second resistors are of resistances sized relative to the second characteristic impedances of the second signal paths so as to substantially minimize test signal reflections at the second nodes. 13. The apparatus in accordance with claim 11 wherein the first, second and third signal paths all have substantially similar impedances. 14. The apparatus in accordance with claim 1 wherein the network comprises:a first node ( 88 ), the first signal path delivering the test signal to the first node;a plurality of second nodes ( 90 , 92 );a plurality of second signal paths ( 42 ), each having a second characteristic impedance being connected for conveying the test signal from the first node to a separate one of the second nodes;plurality of sets of first resistors, each set corresponding to a separate one of the second nodes, each first resistor having a first terminal and a second terminal, the first terminals of all first resistors of each set being to a corresponding one of the second nodes; anda plurality of third transmission lines, each for conveying the test signal from the second terminal of a separate one of the first resistors to a separate one of the probes. 15. The apparatus in accordance with claim 14 wherein the second characteristic impedances of the second signal paths are sized relative to the first impedance of the first signal path to substantially minimize test signal reflections at the first node. 16. The apparatus in accordance with claim 15 wherein a resistance of each first resistor is sized to substantially minimize test signal reflections the second nodes. 17. The apparatus in accordance with claim 1 wherein said first characteristic impedance is less than 150 Ohms. 18. The apparatus in accordance with claim 1 wherein said first characteristic impedance is in a range of 50 to 150 Ohms. 19. An apparatus for providing signal paths between an integrated circuit (IC) tester and a plurality of IC terminals so that a driver within the IC tester can concurrently transmit a test signal to the IC terminals, said test signal exhibiting high and low voltage levels representing logic states, wherein a fault at any one of the IC terminals cond uctively linking that IC terminal to a source of potential can drive that IC terminal near either of said high and low voltage levels, the apparatus comprising:a first signal path having a first characteristic impedance for conveying the test signal away from the driver;a plurality of probes, each for conveying the test signal to a separate one of the plurality of IC terminals; anda probe board assembly comprising:at least one substrate; anda network comprising resistors supported by the at least one substrate, for conveying the test signal from the first signal path to each of the probes,wherein the resistors isolate the IC terminals from one another by an amount of resistance that is substantially larger than the first characteristic impedance of the first signal path and sufficiently large to prevent the fault at any one of the IC terminals from affecting a logic state represented by the test signal at any other of the IC terminals. 20. The apparatus in accordance with claim 19 wherein the probes are attached to the probe board assembly and include tips for contacting the IC terminals. 21. The apparatus in accordance with claim 19 wherein the probes are attached to the IC terminals and include tips for contacting the probe board assembly. 22. The apparatus in accordance with claim 19 wherein the network comprises:a second signal path having a set of taps, the first signal path delivering the test signal to the second signal path, the second signal path conveying the test signal to its taps, wherein the second signal path has a uniform second characteristic impedance between its taps substantially matching the first characteristic impedance of the first signal path;a plurality of first resistors, each having a first terminal connected to a separate one of said taps for receiving the test signal, and having a second terminal, each first resistor conveying the test signal from its first terminal to its second terminal; anda plurality of third signal paths, each conveying the test signal from a separate one of the taps to a separate one of the probes. 23. The apparatus in accordance with claim 19 wherein the network comprises:a first node ( 41 ), the first signal path delivering the test signal to the first node;a plurality of second nodes ( 43 );a plurality of second signal paths ( 42 ), each connected for conveying the test signal from the first node to a separate one of the second nodes, and each second signal path having a second characteristic impedance sized relative to the first characteristic impedance of the first signal path so as to substantially minimize test signal reflections at the first node;a plurality of first resistors;a plurality of sets of third signal paths ( 44 ), each set corresponding to a separate one of the second nodes, each third signal path of each set being connected for conveying the test signal from the set's corresponding second node to a separate one of the first resistors, and each third signal path having a third characteristic impedance sized relative to the second characteristic impedance of the second signal path so as to substantially minimize test signal reflections at the second nodes. 24. The apparatus in accordance with claim 19 wherein the network comprises:a first node ( 66 ), the first signal path delivering the test signal to the first node;a plurality of first resistors ( 67 ), each having a first terminal and a second terminal, the first terminals of all first resistors being connected to the first node such that each resistor conveys the test signal from the first node to its second terminal, wherein the first resistors are of resistances sized relative to the first characteristic impedance of the first signal path so as to substantially minimize test signal reflections at said first node, anda plurality of second signal paths ( 68 ), each linking the second terminal of a separate one of the first resistors to a separate one of the probes. 25. The apparatus in accordance with claim 19 wherein the network comprises:a first node ( 82 ), the first signal path delivering the test signal to the first node;a plurality of first resistors, each having a first terminal and a second terminal, the first terminals of all first resistors being connected to the first node such that each first resistor conveys the test signal from the first node to its second terminal,a plurality of second nodes ( 84 , 86 );a plurality of second signal paths, each having a second characteristic impedance and being linked for conveying the test signal from the first node to a separate one of the second nodes;a plurality of sets of second resistors, each set corresponding to a separate one of the second nodes, each second resistor having a third terminal and a fourth terminal, the third terminals of the second resistors of each set being connected to the set's corresponding second node; anda plurality of third signal paths, each third signal path being connected for conveying the test signal from the second terminal of a separate one of the first resistors to a separate one of the probes,wherein the first resistors are of resistances sized relative to the first characteristic impedance of the first signal path so as to substantially minimize test signal reflections at the first node, andwherein the second resistors are of resistances sized relative to the second characteristic impedances of the second signal paths so as to substantially minimize test signal reflections at the second nodes. 26. The apparatus in accordance with claim 19 wherein the network comprises:a first node ( 88 ), the first signal path delivering the test signal to the first node;a plurality of second nodes ( 90 , 92 );a plurality of second signal paths ( 42 ), each being connected for conveying the test signal from the first node to a separate one of the second nodes, and each having a second characteristic impedances sized relative to the first impedance of the first signal path to substantially minimize test signal reflections at the first node,a plurality of sets of first resistors, each set corresponding to a separate one of the second nodes, each first resistor having a first terminal and a second terminal, the first terminals of all first resistors of each set being to a corresponding one of the second nodes, wherein a resistance of each first resistor is sized to substantially minimize test signal reflections the second nodes; anda plurality of third transmission lines, each for conveying the test signal from the second terminal of a separate one of the first resistors to a separate one of the probes. 27. The apparatus in accordance with claim 19 wherein said first characteristic impedance is less than 150 Ohms. 28. The apparatus in accordance with claim 19 wherein said first characteristic impedance is in a range of 50 to 150 Ohms. 29. The apparatus in accordance with claim 19,wherein said probe board assembly comprises a printed circuit board having a plurality of layers,wherein said network comprises said resistors and traces formed on at least one layer of the printed circuit board and vias passing though the layers of the printed circuit board, andwherein all said traces and vias forming the network have substantially similar characteristic impedances. 30. The apparatus in accordance with claim 19wherein said probe board assembly comprises a plurality of substrates spaced apart from one another, andwherein the network comprises conductors extending between and conveying the test signal through of the substrates. 31. The apparatus in accordance with claim 30 wherein the resistors are mounted on only one of the substrates. 32. The apparatus in accordance with claim 30 wherein the resistors are mounted on more than one of the substrates.