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Method for forming a fin in a finFET device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/8238
출원번호 US-0385753 (2003-03-12)
발명자 / 주소
  • Yang, Chih-Yuh
  • Ahmed, Shibly S.
  • Dakshina-Murthy, Srikanteswara
  • Tabery, Cyrus E.
  • Wang, Haihong
  • Yu, Bin
출원인 / 주소
  • Advanced Micro Devices, Inc.
대리인 / 주소
    Harrity & Snyder, LLP
인용정보 피인용 횟수 : 72  인용 특허 : 2

초록

A method for forming a fin structure on a silicon-on-insulator (SOI) wafer that includes a silicon layer on an insulating layer that is formed over a semiconductor substrate includes etching the silicon layer using a first etch procedure, etching, following the first etch procedure, the silicon laye

대표청구항

1. A semiconductor device, comprising:a substrate;an insulating layer formed on the substrate;a fin structure having a T-shaped cross-section and being formed on a portion of the insulating layer, the fin structure including a lower portion and an upper portion, wherein a width of the upper portion

이 특허에 인용된 특허 (2)

  1. Bin Yu, Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology.
  2. Fried, David M.; Nowak, Edward J.; Rainey, Beth A; Sadana, Devendra K., Fin FET devices from bulk semiconductor and method for forming.

이 특허를 인용한 특허 (72)

  1. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  2. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  3. Ahmed, Shibly S.; Wang, Haihong; Yu, Bin, Damascene gate semiconductor processing with local thinning of channel region.
  4. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
  5. Yeo, Yee-Chia; Wang, Ping-Wei; Chen, Hao-Yu; Yang, Fu-Liang; Hu, Chenming, Doping of semiconductor fin devices.
  6. Yeo, Yee-Chia; Wang, Ping-Wei; Chen, Hao-Yu; Yang, Fu-Liang; Hu, Chenming, Doping of semiconductor fin devices.
  7. Yeo, Yee-Chia; Wang, Ping-Wei; Chen, Hao-Yu; Yang, Fu-Liang; Hu, Chenming, Doping of semiconductor fin devices.
  8. Iwanaga, Junko; Takagi, Takeshi; Kanzawa, Yoshihiko; Sorada, Haruyuki; Saitoh, Tohru; Kawashima, Takahiro, FINFET-type semiconductor device and method for fabricating the same.
  9. Cheng, Kangguo; Khakifirooz, Ali; Reznicek, Alexander; Surisetty, Charan V. V. S., FINFETs with high quality source/drain structures.
  10. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  11. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  12. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  13. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  14. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  15. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  16. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  17. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  18. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  19. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  20. Cheng, Tung-Wen; Chang, Che-Cheng; Lin, Mu-Tsang; Zhang, Zhe-Hao, FinFET and method for manufacturing the same.
  21. Cheng, Kangguo; Khakifirooz, Ali; Reznicek, Alexander; Surisetty, Charan V. V. S., FinFETs with high quality source/drain structures.
  22. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  23. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  24. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  25. Anderson,Brent A.; Nowak,Edward J., Low capacitance junction-isolation for bulk FinFET technology.
  26. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  27. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  28. Liu,David Kuan Yu; Chang,Jonathan Cheang Whang, Method of directionally trimming polysilicon width.
  29. Choi,Jinhan; Deshmukh,Shashank; Yi,Sang; Lee,Kyeong Tae, Method of fabricating a gate structure of a field effect transistor having a metal-containing gate electrode.
  30. Shah,Uday; Doyle,Brian S.; Brask,Justin K.; Chau,Robert S., Method of fabricating a multi-cornered film.
  31. Doyle,Brian S.; Datta,Suman; Kavalieros,Jack T.; Majumdar,Amlan, Method of ion implanting for tri-gate devices.
  32. Loubet, Nicolas; Morin, Pierre, Method of making a semiconductor device using spacers for source/drain confinement.
  33. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  34. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
  35. Liu, Chi-Wen; Wang, Chao-Hsiung, Multi-Fin device and method of making same.
  36. Liu, Chi-Wen; Wang, Chao-Hsiung, Multi-fin device and method of making same.
  37. Liu, Chi-Wen; Wang, Chao-Hsiung, Multi-fin device and method of making same.
  38. Liu, Chi-Wen; Wang, Chao-Hsiung, Multi-fin device and method of making same.
  39. Ahmed,Shibly S.; Wang,Haihong; Yu,Bin, Narrow-body damascene tri-gate FinFET.
  40. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  41. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  42. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  43. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  44. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  45. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  46. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  47. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  48. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  49. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Rios,Rafael; Linton,Tom; Datta,Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
  50. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
  51. Brask,Justin K.; Doyle,Brian S.; Doczy,Mark L.; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
  52. Brask,Justin K.; Doyle,Brian S.; Kavalieros,Jack; Doczy,Mark; Shah,Uday; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
  53. Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  54. Kavalieros,Jack T.; Brask,Justin K.; Doyle,Brian S.; Shah,Uday; Datta,Suman; Doczy,Mark L.; Metz,Matthew V.; Chau,Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  55. Wang,Haihong; Ahmed,Shibly S.; Lin,Ming Ren; Yu,Bin, Reversed T-shaped FinFET.
  56. Wang, Haihong; Ahmed, Shibly S.; Lin, Ming Ren; Yu, Bin, Reversed T-shaped finfet.
  57. Iwanaga, Junko; Takagi, Takeshi; Kanzawa, Yoshihiko; Sorada, Haruyuki; Saitoh, Tohru; Kawashima, Takahiro, Semiconductor device and method for fabricating the same.
  58. Cho, Keun-hwl; Kim, Dong-won; Seo, Jun; Kim, Min-sang; Kim, Sung-min; Bae, Hyun-jun; Lee, Ji-Myoung, Semiconductor device having bar type active pattern.
  59. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  60. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  61. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  62. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  63. Doyle,Brian S; Rakshit,Titash; Chau,Robert S; Datta,Suman; Brask,Justin K; Shah,Uday, Stacked multi-gate transistor design and method of fabrication.
  64. Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
  65. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  66. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  67. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  68. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  69. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  70. Cho, Jun-Hee, Transistor and method for fabricating the same.
  71. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  72. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
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