초록 ▼

A charge/discharge protection circuit with n parallel load current switches and a control logic for the latter, which in an over-voltage event disconnects the battery from the charge/discharge terminals through sequentially controlled melting of integrated fusible links, where the control logic in a

A charge/discharge protection circuit with n parallel load current switches and a control logic for the latter, which in an over-voltage event disconnects the battery from the charge/discharge terminals through sequentially controlled melting of integrated fusible links, where the control logic in an over-voltage event, simultaneously closes all load current switches, then following sequentially opens a first number of the load current switches, and at the same time closes the switch segments of a short-circuit switch array associated with the respective load current switch, so that the associated fusible links melt sequentially. After the opening of this first number of load current switches the latter closes again and at the same time the remaining number of still closed load current switches opens, as well as continues to sequentially close the remaining switch segments.

대표청구항 ▼

1. A charge/discharge protection circuit for a battery, comprising:a protection circuit having a first, a second, and a third terminal, where said first and said second terminal are coupled to battery terminals of at least one rechargeable cell, where said second and said third terminal are coupled

1. A charge/discharge protection circuit for a battery, comprising:a protection circuit having a first, a second, and a third terminal, where said first and said second terminal are coupled to battery terminals of at least one rechargeable cell, where said second and said third terminal are coupled to charge/discharge terminals of an external device, said protection circuit protecting said battery from an over-voltage from said external device, said protection circuit further comprising:a first serial circuit comprising a fusible link and a load current switch, said first serial circuit coupled between said first terminal and said third terminal, where said load current switch is controlled by a control logic, and where a plurality n of said first serial circuits are coupled in parallel, such that there are n said fusible links and n said load current switches;a second serial circuit comprising a switch segment, where said second serial circuit is coupled between the junction of said fusible link and said load current switch and said second terminal, where said switch segment is controlled by said control logic, and where a plurality n of such second serial circuits are coupled in parallel, such that there are n switch segments, where the plurality n of such switch segments is called a short-circuit switch array; andsaid control logic coupled between said second and said third terminal, said control logic detecting the conditions of under-voltage and over-voltage at said first and said second terminals, over-current, under-current, and over-voltage at said second and said third terminals, where said control logic generates first and second control signals in response to said conditions, such that said first control signal controls the opening and closing of each of said switch segments of said short-circuit switch array and said second control signal controls the opening and closing of each of said load current switches, were said second control signal causes all n of said load current switches to open simultaneously, thereby separating said battery from said external device, were, upon detecting an over-voltage at said second and said third terminals, said first and said second signal causes all n of said load current switches to close simultaneously, then to open sequentially said short-circuit switch array, thereby causing to melt sequentially all n of said fusible links, to open immediately and sequentially a first number of said load current switches after having closed all n of them earlier, following the opening of the last of said first number of said load current switches to then close simultaneously said first number of said load current switches, which then is followed by the simultaneous opening of the second remaining number of said load current switches. 2. The charge/discharge protection circuit-of claim 1, wherein at least those circuit components of said control logic which generate said first control signal for said short-circuit switch array receive their supply voltage from an auxiliary voltage source. 3. The charge/discharge protection circuit of claim 2, wherein said auxiliary voltage source is charged via a semiconductor circuit to the battery voltage, where said semiconductor circuit switches to its non-conductive state when said battery voltage falls below a predetermined value. 4. The charge/discharge protection circuit of claim 3, wherein said semiconductor circuit switches to its non-conductive state when said over-voltage at said second and said third terminal is detected. 5. The charge/discharge protection circuit of claim 2, wherein said auxiliary voltage source is charged via a charge pump to the maximally allowable operating voltage for said control logic. 6. The charge/discharge protection circuit of claim 2, wherein said auxiliary voltage source is a buffer capacitor. 7. A charge/discharge protection circuit for a battery, comprising:a protection circuit having a first, a second, and a third terminal, where said first and said second terminal are coupled to the battery terminals of at least one rechargeable cell, where said second and said third terminal are coupled to the charge/discharge terminals of an external device, said protection circuit protecting said battery from an over-voltage from said external device, said protection circuit further comprising:a first serial circuit comprising a fusible link and a load current switch, said first serial circuit coupled between said first terminal and said third terminal, where said load current switch is controlled by a control logic, and where a plurality n of said first serial circuits are coupled in parallel, such that there are n said fusible links and n said load current switches;a second serial circuit comprising a switch segment, where said second serial circuit is coupled between the junction of said fusible link and said load current switch and said second terminal, where said switch segment is controlled by said control logic, and where a plurality n of such second serial circuits are coupled in parallel, such that there are n switch segments, where the plurality n of such switch segments is defined as a short-circuit switch array; andsaid control logic coupled between said second and said third terminal, said control logic further comprising an over-voltage detector and a digital switching circuit, where said control logic generates a first error signal when detecting the conditions of under-voltage and over-voltage at said first and said second terminals, over-current and under-current at said second and said third terminals, where said digital switching circuit generates with input from said over-voltage detector a second error signal when detecting the condition of over-voltage at said second and said third terminals, where said first and said second error signal are inputs to said digital switching circuit, where said digital switching circuit generates a first and a second control signal, such that said first control signal controls the opening and closing of each of said switch segments of said short-circuit switch array and said second control signal controls the opening and closing of each of said load current switches, such that when only said first error signal is active it causes all said load current switches to open simultaneously, thereby separating said battery from said external device, and such that when only said second error signal is active it causes all n of said load current switches to close simultaneously, then to open sequentially said short-circuit switch array, thereby causing to melt sequentially all n of said fusible links, to open sequentially a first number of said load current switches immediately after having closed all n of them earlier, then following the opening of the last of said first number of said load current switches to close simultaneously said first number of said load current switches, which then is followed by the simultaneous opening of the second remaining number of said load current switches. 8. The charge/discharge protection circuit of claim 7, wherein at least those circuit components of said control logic which generate said first control signal for said short-circuit switch array receive their supply voltage from an auxiliary voltage source. 9. The charge/discharge protection circuit of claim 8, wherein said auxiliary voltage source is charged via a semiconductor circuit to the battery voltage, where said semiconductor circuit switches to its non-conductive state when said battery voltage falls below a predetermined value. 10. The charge/discharge protection circuit of claim 9, wherein said semiconductor circuit switches to its non-conductive state when said over-voltage at said second and said third terminal is detected. 11. The charge/discharge protection circuit of claim 8, wherein said auxiliary voltage source is charged via a charge pump to the maximally allowable operating voltage for said contr ol logic. 12. The charge/discharge protection circuit of claim 8, wherein said auxiliary voltage source is a buffer capacitor. 13. The charge/discharge protection circuit of claim 7, wherein said over-voltage detector comprises a bistable flip-flop circuit which switches into its second stable state in an over-voltage event. 14. The charge/discharge protection circuit of claim 7, wherein said digital switching circuit comprises a plurality of successive bistable flip-flop circuits equal in number to said number n of said load current switches and switch segments to be controlled. 15. The charge/discharge protection circuit of claim 7, wherein said digital switching circuit comprises a clock generator, where said clock generator is enabled by said second error signal. 16. The charge/discharge protection circuit of claim 15, wherein said bistable flip-flop circuits are switched sequentially into their second stable state via a clock signal issued by said clock generator. 17. The charge/discharge protection circuit of claim 14, wherein the outputs of said bistable flip-flop circuits deliver said first and said second control signal. 18. The charge/discharge protection circuit of claim 7, wherein, with the exception of capacitors, all circuit components are integrated on a chip.