초록 ▼

An approach for cut-point frontier selection and/or counter-example generation. Both a lazy and an eager cut-point frontier are identified. A reconvergence (or non-reconvergence) ratio is then computed for each of the frontiers and the one with the smaller (larger) reconvergence (non-reconvergence)

An approach for cut-point frontier selection and/or counter-example generation. Both a lazy and an eager cut-point frontier are identified. A reconvergence (or non-reconvergence) ratio is then computed for each of the frontiers and the one with the smaller (larger) reconvergence (non-reconvergence) ratio is selected as the next cut-point frontier. For another aspect, to generate a counter-example, in response to identifying a difference in output signals for a given cut-point frontier, values of eigenvariables and reconverging primary inputs are used to compute the corresponding values of the non-reconverging primary inputs. These corresponding values are then computed to be compatible with the internal signal values implied by the cut-point frontier selections that were made to expose the difference in the outputs.

대표청구항 ▼

1. A method comprising:for an integrated circuit model, identifying a lazy cut-point frontier and an eager cut-point frontier, the lazy cut-point frontier being one of inputs of the model and a cut-point frontier closest to a prior cut-point frontier and the eager cut-point frontier being a cut-poin

1. A method comprising:for an integrated circuit model, identifying a lazy cut-point frontier and an eager cut-point frontier, the lazy cut-point frontier being one of inputs of the model and a cut-point frontier closest to a prior cut-point frontier and the eager cut-point frontier being a cut-point frontier closest to outputs of the model, each of the lazy and eager cut-point frontiers being associated with a set of variables indicating signal lines that pass through the respective cut-point frontier;computing a ratio of one of reconverging and non-reconverging variables to a total number of variables for each of the identified lazy and eager cut-point frontiers, a reconverging variable identifying a signal line that has a fanout leading to an output of the integrated circuit model by going outside of a logic cone of the signal line, a non-reconverging variable identifying a signal line that does not have a fanout leading to an output of the integrated circuit model by going outside of a logic cone of the signal line; andselecting from the lazy and eager cut-paint frontiers based on the computed ratios. 2. The method of claim 1 whereincomputing a ratio comprises computing a ratio of reconverging variables to a total number of variables (reconvergence ratio), andwherein selecting comprises selecting the cut-point frontier with the smallest reconvergence ratio. 3. The method of claim 1 whereincomputing a ratio comprises computing a ratio of non-reconverging variables to a total number of variables (non-reconvergence ratio), andwherein selecting comprises selecting the cut-point frontier with the largest non-reconvergence ratio. 4. The method of claim 1 whereinidentifying a lazy cut-point frontier and an eager cut-point frontier includes identifying the lazy and eager cut-point frontiers based on cut-points identified in a specification circuit model and an implementation circuit model. 5. The method of claim 4 wherein identifying a lazy cut-point frontier and an eager cut-point frontier includes identifying the lazy and eager cut-point frontiers based on cut-points identified in a specification circuit model in a hardware description language and a schematic. 6. A machine-accessible storage medium storing instructions that, when accessed by a machine, cause the machine to perform:identifying a lazy cut-point frontier and an eager cut-point frontier for an integrated circuit model, the lazy cut-point frontier being one of inputs of the model and a cut-point frontier closest to a prior cut-point frontier and the eager cut-point frontier being a cut-point frontier closest to outputs of the model, each of the lazy and eager cut-point frontiers being associated with a set of variables indicating signal lines that pass through the respective cut-point frontier;computing a ratio of one of reconverging and non-reconverging variables to a total number of variables for each of the identified lazy and eager cut-point frontiers, a reconverging variable identifying a signal line that has a fanout leading to an output of the integrated circuit model by going outside of a logic cone of the signal line, a non-reconverging variable identifying a signal line that does not have a fanout leading to an output of the integrated circuit model by going outside of a logic cone of the signal line; andselecting from the lazy and eager cut-point frontiers based on the computed ratios. 7. The machine-accessible storage medium of claim 6 whereincomputing a ratio comprises computing a ratio of reconverging variables to a total number of variables (reconvergence ratio), andwherein selecting comprises selecting the cut-point frontier with the smallest reconvergence ratio. 8. The machine-accessible storage medium of claim 6 whereincomputing a ratio comprises computing a ratio of non-reconverging variables to a total number of variables (non-reconvergence ratio), andwherein selecting comprises selecting the cut-point frontier with the largest non-reconvergence ratio. 9. An apparatus comprising:an input to receive integrated circuit models to be formally verified; anda cut-point frontier selection engine to identify an eager and a lazy cut-point frontiers, the lazy cut-point frontier being one of inputs of the model and a cut-point frontier closest to a prior cut-point frontier and the eager cut-point frontier being a cut-point frontier closest to outputs of the model, each of the lazy and eager cut-point frontiers being associated with a set of variables indicating signal lines that pass through the respective cut-point frontier, to compute one of a reconvergence and a non-reconvergence ratio for each of the identified cut-point frontiers, a reconvergence ratio being a ratio of reconverging variables to a total number of variables associated with the respective cut-point frontier, a non-reconvergence ration being a ratio of non-reconverging variables to a total number of variables associated with the respective cut-point frontier, a reconverging variable identifying a signal line that has a fanout leading to an output of the integrated circuit model by going outside of a logic cone of the signal line, a non-reconverging variable identifying a signal line that does not have a fanout leading to an output of the integrated circuit model by going outside of a logic cone of the signal line and to select between the identified eager and the lazy cut-point frontiers based on the computed ratios. 10. The apparatus of claim 9 whereinthe cut-point frontier selection engine is to compute a reconvergence ratio for each of the identified cut-paint frontiers and to select the cut-point frontier with the smallest reconvergence ratio. 11. The apparatus of claim 9 whereinthe cut-point frontier selection engine is to compute a non-reconvergence ratio for each of the identified cut-point frontiers end to select the cut-point frontier with the largest non-reconvergence ratio. 12. The apparatus of claim 9 further comprising:a counter-example generation engine, the counter-example generation engine to identify values of variables for inputs to the circuit models that cause the circuit models to produce results that are different from each other. 13. The apparatus of claim 12 whereinthe counter-example generation engine is to identify the values based on the values of eigenvariables and reconverging primary inputs associated with a sequence of cut-point frontier selections that causes a difference in the outputs of the circuit models. 14. The apparatus of claim 9 wherein a first one of the integrated circuit models is a specification circuit model and the second one of the circuit models is an implementation circuit model. 15. The apparatus of claim 14 wherein the specification model is specified in a hardware description language and the implementation circuit model is a schematic.