초록 ▼

An access transaction generated by a processor is configured using a configuration storage containing a configuration setting. The processor has a normal execution mode and an isolated execution mode. The access transaction has access information. Access to the configuration storage is controlled. A

An access transaction generated by a processor is configured using a configuration storage containing a configuration setting. The processor has a normal execution mode and an isolated execution mode. The access transaction has access information. Access to the configuration storage is controlled. An access grant signal is generated using the configuration setting and the access information. The access grant signal indicates if the access transaction is valid.

대표청구항 ▼

1. An apparatus comprising:a configuration storage containing a configuration setting to configure an access transaction generated by a processor having a normal execution mode and an isolated execution mode, the access transaction having access information;a configuration controller coupled to the

1. An apparatus comprising:a configuration storage containing a configuration setting to configure an access transaction generated by a processor having a normal execution mode and an isolated execution mode, the access transaction having access information;a configuration controller coupled to the configuration storage to control access to the configuration storage; andan access grant generator coupled to the configuration storage to generate an access grant signal using the configuration setting and the access information, the access grant signal indicating if the access transaction is valid. 2. The apparatus of claim 1 wherein the configuration setting includes a memory mask value and a memory base value, the memory mask and base values defining an isolated memory area in a memory external to the processor, the isolated memory area being accessible to the processor in the isolated execution mode. 3. The apparatus of claim 2 wherein the configuration storage comprises:a memory mask register to store the memory mask value; anda memory base register to store the memory base value. 4. The apparatus of claim 3 wherein the access information includes a physical address and an isolated access state, the isolated access state being provided by an isolated access signal, the isolated access signal being asserted when the processor generates a valid reference to the isolated memory area. 5. The apparatus of claim 4 wherein the configuration controller comprises:a control storage to store a lock control word, the lock control word indicating if the isolated memory area is enabled; anda locker to lock access to the configuration storage based on the lock control word. 6. The apparatus of claim 5 wherein the configuration controller further comprises:a prioritizer to prioritize the access transaction based on the lock control word. 7. The apparatus of claim 6 wherein the configuration controller further comprises:a resetter to initialize the isolated memory area, the configuration storage, and the control storage upon reset. 8. The apparatus of claim 7 wherein the access grant generator comprises:an address detector to detect if the physical address is within the isolated memory area, the address detector generating an address matching signal; andan access grant combiner coupled to the address detector to combine the address matching signal and the isolated access signal, the combined address matching signal and the isolated access signal corresponding to the access grant signal. 9. The apparatus of claim 8 wherein the address detector comprises:a masking element to mask the physical address with the memory masking value; anda comparator to compare the masked physical address with the memory base value, the comparator generating a matching result corresponding to the address matching signal. 10. The apparatus of claim 9 wherein the address detector further comprises:an address detect combiner to combine the matching result with at least one access condition, the combined matching result and the at least one access condition providing the address matching signal. 11. A method comprising:configuring an access transaction generated by a processor having a normal execution mode and an isolated execution mode using a configuration storage containing a configuration setting, the access transaction having access information;controlling access to the configuration storage; andgenerating an access grant signal using the configuration setting and the access information, the access grant signal indicating if the access transaction is valid. 12. The method of claim 11 wherein the configuration setting includes a memory mask value and a memory base value, the memory mask and base values defining an isolated memory area in a memory external to the processor, the isolated memory area being accessible to the processor in the isolated execution mode. 13. The method of claim 12 wherein configuring the access transaction comprises:storing the memory mask value in a memory mask register; andstoring the memory base value in a memory base register. 14. The method of claim 13 wherein the access information includes a physical address and an isolated access state, the isolated access state being provided by an isolated access signal, the isolated access signal being asserted when the processor generates a valid reference to the isolated memory area. 15. The method of claim 14 wherein controlling access to the configuration storage comprises:storing a lock control word, the lock control word indicating if the isolated memory area is enabled; andlocking access to the configuration storage based on the lock control word. 16. The method of claim 15 wherein controlling access to the configuration storage further comprises:prioritizing the access transaction based on the lock control word. 17. The method of claim 16 wherein controlling access to the configuration storage further comprises:initializing the isolated memory area, the configuration storage, and the control storage upon reset. 18. The method of claim 17 wherein generating the access grant signal comprises:generating an address matching signal indicating if the physical address is within the isolated memory area; andcombining the address matching signal and the isolated access signal, the combined address matching signal and the isolated access signal corresponding to the access grant signal. 19. The method of claim 18 wherein generating the address matching signal comprises:masking the physical address with the memory masking value; andcomparing the masked physical address with the memory base value to generate a matching result corresponding to the address matching signal. 20. The method of claim 19 wherein generating the address matching signal further comprises:combining the matching result with at least one access condition, the combined matching result and the at least one access condition providing the address matching signal. 21. A computer program product comprising:a machine readable medium having computer program code therein, the computer program product comprising:computer readable program code for configuring an access transaction generated by a processor having a normal execution mode and an isolated execution mode using a configuration storage containing a configuration setting, the access transaction having access information;computer readable program code for controlling access to the configuration storage; andcomputer readable program code for generating an access grant signal using the configuration setting and the access information, the access grant signal indicating if the access transaction is valid. 22. The computer program product of claim 21 wherein the configuration setting includes a memory mask value and a memory base value, the memory mask and base values defining an isolated memory area in a memory external to the processor, the isolated memory area being accessible to the processor in the isolated execution mode. 23. The computer program product of claim 22 wherein the computer readable program code for configuring the access transaction comprises:computer readable program code for storing the memory mask value in a memory mask register; andcomputer readable program code for storing the memory base value in a memory base register. 24. The computer program product of claim 23 wherein the access information includes a physical address and an isolated access state, the isolated access state being provided by an isolated access signal, the isolated access signal being asserted when the processor generates a valid reference to the isolated memory area. 25. The computer program product of claim 24 wherein the computer readable program code for controlling access to the configuration storage comprises:computer readable program code for storing a lock control word, the lock control word indicating if the isolated memory area is enabled; andcomputer readable program code for locking access to the confi guration storage based on the lock control word. 26. The computer program product of claim 25 wherein the computer readable program code for controlling access to the configuration storage further comprises:computer readable program code for prioritizing the access transaction based on the lock control word. 27. The computer program product of claim 26 wherein the computer readable program code for controlling access to the configuration storage further comprises:computer readable program code for initializing the isolated memory area, the configuration storage, and the control storage upon reset. 28. The computer program product of claim 27 wherein the computer readable program code for generating the access grant signal comprises:computer readable program code for generating an address matching signal indicating if the physical address is within the isolated memory area; andcomputer readable program code for combining the address matching signal and the isolated access signal, the combined address matching signal and the isolated access signal corresponding to the access grant signal. 29. The computer program product of claim 28 wherein the computer readable program code for generating the address matching signal comprises:computer readable program code for masking the physical address with the memory masking value; andcomputer readable program code for comparing the masked physical address with the memory base value to generate a matching result corresponding to the address matching signal. 30. The computer program product of claim 29 wherein the computer readable program code for generating the address matching signal further comprises:computer readable program code for combining the matching result with at least one access condition, the combined matching result and the at least one access condition providing the address matching signal. 31. A system comprising:a processor having a normal execution mode and an isolated execution mode;a memory coupled to the processor having an isolated memory area accessible to the processor in the isolated execution mode; anda chipset coupled to the memory having an access controller, the access controller comprising:a configuration storage containing a configuration setting to configure an access transaction generated by the processor, the access transaction having access information,a configuration controller coupled to the configuration storage to control access to the configuration storage, andan access grant generator coupled to the configuration storage to generate an access grant signal using the configuration setting and the access information, the access grant signal indicating if the access transaction is valid. 32. The system of claim 31 wherein the configuration setting includes a memory mask value and a memory base value, the memory mask and base values defining the isolated memory area in the memory. 33. The system of claim 32 wherein the configuration storage comprises:a memory mask register to store the memory mask value; anda memory base register to store the memory base value. 34. The system of claim 33 wherein the access information includes a physical address and an isolated access state, the isolated access state being provided by an isolated access signal, the isolated access signal being asserted when the processor generates a valid reference to the isolated memory area. 35. The system of claim 34 wherein the configuration controller comprises:a control storage to store a lock control word, the lock control word indicating if the isolated memory area is enabled; anda locker to lock access to the configuration storage based on the lock control word. 36. The system of claim 35 wherein the configuration controller further comprises:a prioritizer to prioritize the access transaction based on the lock control word. 37. The system of claim 36 wherein the configuration controller further comprises:a resetter to initialize the isolated memory area, the configuration storag e, and the control storage upon reset. 38. The system of claim 37 wherein the access grant generator comprises:an address detector to detect if the physical address is within the isolated memory area, the address detector generating an address matching signal; andan access grant combiner coupled to the address detector to combine the address matching signal and the isolated access signal, the combined address matching signal and the isolated access signal corresponding to the access grant signal. 39. The system of claim 38 wherein the address detector comprises:a masking element to mask the physical address with the memory masking value; anda comparator to compare the masked physical address with the memory base value, the comparator generating a matching result corresponding to the address matching signal. 40. The system of claim 39 wherein the address detector further comprises:an address detect combiner to combine the matching result with at least one access condition, the combined matching result and the at least one access condition providing the address matching signal.