[특허]Method of Interconnecting substrates for electrical coupling of microelectronic components

[미국특허] Method of Interconnecting substrates for electrical coupling of microelectronic components 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01K-003/10
출원번호	US-0266847 (2002-10-07)
발명자 / 주소	Ahmad, Syed Sajid
출원인 / 주소	Micron Technology, Inc.
대리인 / 주소	Perkins Coie LLP
인용정보	피인용 횟수 : 7 인용 특허 : 145

초록 ▼

Interconnecting substrates used in the manufacturing of microelectronic devices and printed circuit assemblies, packaged microelectronic devices having interconnecting substrates, and methods of making and using such interconnecting substrates. In one aspect of the invention, an interconnecting substrate comprises a first external layer having a first external surface, a second external layer having a second external surface, and a conductive core between the first and second external layers. The conductive core can have at least a first conductive stratum between the first and second external layers, and a dielectric layer between the first conductive stratum and one of the first or second external layers. The conductive core can also include a second conductive stratum such that the first conductive stratum is on a first surface of the dielectric layer and the second conductive stratum is on a second surface of the dielectric layer. The interconnecting substrate also has at least one vent through at least one of the first conductive stratum, the second conductive stratum, and/or the dielectric layer. The vent is configured to direct moisture away from the dielectric layer, and thus the vent can be a moisture release element that allows moisture to escape from the dielectric layer during high temperature processing.

대표청구항 ▼

1. A method of manufacturing an interconnecting substrate, comprising:constructing an internal conductive core by disposing a first conductive stratum on a first surface of a dielectric layer;forming at least one vent in at least one of the first conductive stratum and/or the dielectric layer, the vent being configured to direct moisture away from the dielectric layer; andlaminating the internal conductive core between a first external layer and a second external layer. 2. The method of claim 1 wherein constructing the internal conductive core further comprises disposing a second conductive stratum on a second surface of the dielectric layer, the second surface being opposite the first surface. 3. The method of claim 1 wherein:constructing the internal conductive core further comprises disposing a second conductive stratum on a second surface of the dielectric layer, the second surface being opposite the first surface; andforming at least one vent comprises creating a first hole in the first conductive stratum and creating a second hole in the second conductive stratum. 4. The method of claim 3 wherein:disposing the first conductive layer comprises forming a ground plane by covering the first surface of the dielectric layer with a first metal layer;disposing the second conductive layer comprises forming a power plane by covering the second surface of the dielectric layer with a second metal layer; andcreating the first hole comprises etching the first hole in the first metal layer and creating the second hole comprises etching the second hole in the second metal layer. 5. The method of claim 1 wherein:constructing the internal conductive core further comprises disposing a second conductive stratum on a second surface of the dielectric layer, the second surface being opposite the first surface; andforming at least one vent comprises creating a first channel in the first conductive stratum and creating a second channel in the second conductive stratum. 6. The method of claim 5 wherein:disposing the first conductive layer comprises forming a ground plane by covering the first surface of the dielectric layer with a first metal layer;disposing the second conductive layer comprises forming a power plane by covering the second surface of the dielectric layer with a second metal layer; andcreating the first channel comprises etching the first channel in the first metal layer and creating the second channel comprises etching the second channel in the second metal layer.

이 특허에 인용된 특허 (145) 인용/피인용 타임라인 분석

King Jerrold L. ; Brooks J. Mike ; Moden Walter L., Adhesion enhanced semiconductor die for mold compound packaging.
상세보기
Mess Leonard E. ; Corisis David J. ; Moden Walter L. ; Kinsman Larry D., Apparatus and methods of packaging and testing die.
상세보기
Saxelby ; Jr. John R. ; Hedlund ; III Walter R., Apparatus for circuit encapsulation.
상세보기
Weber Patrick O. (San Jose CA), Apparatus for encapsulating electronic packages.
상세보기
Thummel Steven G., Apparatus for encasing array packages.
상세보기
Akram Salman, Apparatus for packaging flip chip bare die on printed circuit boards.
상세보기
Johnson Mark S. ; Bolken Todd O., Asymmetric transfer molding method and an asymmetric encapsulation made therefrom.
상세보기
Moden Walter, BGA package and method of fabrication.
상세보기
Castro Abram M., Ball grid substrate for lead-on-chip semiconductor package.
상세보기
Corisis David ; Moden Walter, Chip package.
상세보기
Corisis David J., Chip scale package with heat spreader and method of manufacture.
상세보기
Hembree David R. ; Akram Salman, Circuit and method for heating an adhesive to package or rework a semiconductor die.
상세보기
John R. Saxelby, Jr. ; Walter R. Hedlund, III, Circuit encapsulation.
상세보기
Saxelby ; Jr. John R. ; Hedlund ; III Walter R., Circuit encapsulation process.
상세보기
Tandy Patrick W. ; Brand Joseph M. ; Rumsey Brad D. ; Stephenson Steven R. ; Corisis David J. ; Bolken Todd O. ; Schrock Edward A. ; Dickey Brenton L., Controlling packaging encapsulant leakage.
상세보기
Ahmad Syed Sajid, Die positioning in integrated circuit packaging.
상세보기
Wood Alan G. ; Farnworth Warren M. ; Grigg Ford ; Akram Salman, Direct die contact (DDC) semiconductor package.
상세보기
Wood Alan G. ; Farnworth Warren M. ; Grigg Ford ; Akram Salman, Direct die contact (DDC) semiconductor package.
상세보기
SinghDeo Narendra N. (New Haven CT) Mahulikar Deepak (Meriden CT) Butt Sheldon H. (Godfrey IL), Electronic packaging of components incorporating a ceramic-glass-metal composite.
상세보기
Wensel Richard W., Encapsulated integrated circuit packaging.
상세보기
Poinelli Renato,ITX ; Corno Marziano,ITX, Heat-dissipating and supporting structure for a plastic package with a fully insulated heat sink for an electronic devi.
상세보기
Nambu Seigo (Tokyo JPX) Takei Shinji (Tokyo JPX) Okuaki Hiroshi (Tokyo JPX), Heat-resistant plastic semiconductor device.
상세보기
Farnworth Warren M., Hermetically sealed chip scale packages formed by wafer level fabrication and assembly.
상세보기
Chang Chi S. (Endicott) Hoffarth Joseph G. (Binghamton) Markovich Voya R. (Endwell) Snyder Keith A. (Vestal) Wiley John P. (Vestal NY), High density circuit board and method of making same.
상세보기
Farnworth Warren M. ; Akram Salman ; Wood Alan G. ; Brooks Mike ; Cloud Eugene, High density semiconductor package.
상세보기
Combs Edward G. (Foster City CA), High power dissipation plastic encapsulated package for integrated circuit die.
상세보기
Corisis David J. ; Keeth Brent, High speed IC package configuration.
상세보기
Fox ; III Angus C. (Boise ID) Farnworth Warren M. (Nampa ID), High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vi.
상세보기
Mazumder Mohiuddin M., Hole geometry of a semiconductor package substrate.
상세보기
Corisis David J., IC package with dual heat spreaders.
상세보기
Corisis David J. ; Reynolds Tracy ; Slaughter Michael ; Cram Daniel ; Nevill Leland R. ; King Jerrold L., Integrated circuit package alignment feature.
상세보기
Akram Salman ; Farnworth Warren M., Integrated circuit package and method of fabrication.
상세보기
Matsumoto Kazuhiro (Tokyo JPX), Integrated circuit package having stress reducing recesses.
상세보기
Corisis David J. ; Reynolds Tracy ; Slaughter Michael ; Cram Daniel ; Nevill Leland R. ; King Jerrold L., Integrated circuit package including lead frame with electrically isolated alignment feature.
상세보기
Manzione Louis T. (Summit) Patel C. Kumar (Summit NJ), Integrated circuit package with strain relief grooves.
상세보기
Syed Sajid Ahmad, Interconnecting substrates for electrical coupling of microelectronic components.
상세보기
Corisis David J. ; Brooks Jerry M. ; Lee Terry R., Lead frame assemblies with voltage reference plane and IC packages including same.
상세보기
Japp Robert M. ; Poliks Mark D., Low CTE power and ground planes.
상세보기
Kinsman Larry D., Low profile ball grid array package.
상세보기
Moden Walter L. ; King Jerrold L. ; Brooks Jerry M., Low profile multi-IC chip package connector.
상세보기
Shintai Akira,JPX, Manufacturing method for a resin sealed semiconductor device.
상세보기
Farnworth Warren ; Kinsman Larry ; Moden Walter, Method and apparatus for a semiconductor package for vertical surface mounting.
상세보기
Akram Salman, Method and apparatus for packaging flip chip bare die on printed circuit boards.
상세보기
Phillips Eugene (Diamond Bar CA), Method for conditioning drilled holes in multilayer wiring boards.
상세보기
Variot Patrick (San Jose CA), Method for encapsulating an integrated circuit package.
상세보기
Ishii Masaaki,JPX, Method for encapsulation of semiconductor devices with resin and leadframe therefor.
상세보기
Thummel Steven G., Method for encasing array packages.
상세보기
Jiang Tongbi ; Schrock Edward, Method for fabricating BGA package using substrate with patterned solder mask open in die attach area.
상세보기
Bolken Todd O. ; Peters David L. ; Tandy Patrick W. ; Cobbley Chad A., Method for fabricating semiconductor packages using mold tooling fixture with flash control cavities.
상세보기
McShane Michael B. (Austin TX) Casto James J. (Austin TX) Joiner Bennett A. (Austin TX), Method for making a thermally enhanced semiconductor device by holding a leadframe against a heatsink through vacuum suc.
상세보기
Djennas Frank (Austin TX) Nomi Victor K. (Round Rock TX) Pastore John R. (Leander TX) Reeves Twila J. (Austin TX) Postlethwait Les (Lexington TX), Method for making semiconductor device having no die supporting surface.
상세보기
Odashima Teikou,JPX ; Matsui Mikio,JPX ; Sugizaki Yoshiaki,JPX ; Nakazawa Takahito,JPX, Method for manufacturing semiconductor device and apparatus for resin-encapsulating.
상세보기
Drummond Brian (Austin TX), Method for molding using venting pin.
상세보기
Kinsman Larry D. (Boise ID), Method for packaging a semiconductor die.
상세보기
Farnworth Warren M. (Nampa ID) Wood Alan G. (Boise ID) Doan Trung T. (Boise ID) Jacobson John O. (Boise ID), Method for packaging semiconductor dice.
상세보기
Farnworth Warren M. ; Wood Alan G. ; Hembree David R. ; Akram Salman, Method for testing semiconductor dice with conventionally sized temporary packages.
상세보기
Manzione Louis T. (Summit NJ) Weld John D. (Succasunna NJ), Method of encapsulating large substrate devices using reservoir cavities for balanced mold filling.
상세보기
Taniguchi Fumihiko,JPX ; Honna Koji,JPX ; Kumagaya Yoshikazu,JPX, Method of fabricating semiconductor having through hole.
상세보기
Farnworth Warren M., Method of forming overmolded chip scale package and resulting product.
상세보기
Brooks Jerry M. ; Thummel Steven G., Method of making a cavity ball grid array apparatus.
상세보기
Schachter Herbert I. (86 Campbell St. New Hyde Park ; Long Island NY 11040), Method of making a multi-level circuit board.
상세보기
King Jerold L. ; Brooks Jerry M., Method of making a multichip semiconductor package.
상세보기
Rose Ren (Voisin-Le-Bretonneux FRX), Method of making an electronic module for a memory card and an electronic module thus obtained.
상세보기
Knapp James H. ; Scribner Cliff J. ; Laninga ; Sr. Albert J., Method of manufacturing a semiconductor component.
상세보기
Crowley Sean T. ; Cheney Gerald L. ; Razu David S., Method of molding plastic semiconductor packages.
상세보기
Chun Hung Lin TW, Method of molding semiconductor device and molding die for use therein.
상세보기
Sakai Kunito (Hyogo JPX) Matsuda Sadamu (Hyogo JPX) Takahama Takashi (Hyogo JPX), Method of resin encapsulating a semiconductor device.
상세보기
Leonard E. Mess, Methods for ball grid array (BGA) encapsulation mold.
상세보기
Tripard Jason E., Methods of forming integrated circuit packages.
상세보기
Akram Salman ; Hembree David R. ; Farnworth Warren M., Micromachined chip scale package.
상세보기
Akram Salman ; Hembree David R. ; Farnworth Warren M., Micromachined chip scale package.
상세보기
Chia Chok J. (Campbell CA) Lim Seng-Sooi (San Jose CA), Modified lead frame for reducing wire wash in transfer molding of IC packages.
상세보기
Farnworth Warren M. ; Corisis David J. ; Akram Salman, Modular die sockets with flexible interconnects for packaging bare semiconductor die.
상세보기
Miles Barry M. ; Mullen ; III William B. ; Gold Glenn E., Moisture enhanced ball grid array package.
상세보기
Freyman Bruce J. (Plantation FL) Juskey Frank J. (Coral Springs FL) Miles Barry M. (Plantation FL), Moisture relief for chip carrier.
상세보기
Miles Barry M., Moisture relief for chip carriers.
상세보기
Lee Sang S. ; Loh William M., Mold flow regulating dam ring.
상세보기
Chia Chok J. ; Lim Seng-Sooi ; Low Qwai H., Molded array integrated circuit package.
상세보기
Weld John David, Molded encapsulated electronic component.
상세보기
Izumi Atsuhiko (Tokyo JPX) Inaba Takehito (Tokyo JPX) Azuma Kousuke (Tokyo JPX), Molding die for sealing semiconductor device with reduced resin burrs.
상세보기
Kao-Yu Hsu TW; Chun Hung Lin TW; Tao-Yu Chen TW, Molding method for BGA semiconductor chip package.
상세보기
Jain Praveen (Gilbert AZ) Kar Rudra (Mesa AZ), Molding technique for molding plastic packages.
상세보기
Ferri Stefano,ITX ; Rossi Roberto,ITX, Package for electronic device having a fully insulated dissipator.
상세보기
Tandy Patrick W., Package stack via bottom leaded plastic (BLP) packaging.
상세보기
Akram Salman ; Wark James M., Packaged die on PCB with heat sink encapsulant.
상세보기
Bolken Todd O. ; Baerlocher Cary J. ; Corisis David J. ; Cobbley Chad A., Packages for semiconductor die.
상세보기
Hodges Joe W., Packaging for bare dice employing EMR-sensitive adhesives.
상세보기
Wood Alan G. (Boise ID) Corbett Tim J. (Boise ID), Packaging for semiconductor logic devices.
상세보기
Wood Alan G. ; Corbett Tim J., Packaging for semiconductor logic devices.
상세보기
Kinsman Larry (Boise ID), Packaging means for a semiconductor die having particular shelf structure.
상세보기
Jiang Tongbi ; Yin Zhiping, Passivation layer for packaged integrated circuits.
상세보기
Nambu Seigo (Tokyo JPX) Fukazawa Hiroyuki (Tokyo JPX) Takei Shinji (Tokyo JPX), Plastic-sealed IC device of heat-resistant construction.
상세보기
Wang Kuo K. ; Han Sejin, Pressurized underfill encapsulation of integrated circuits.
상세보기
Ha Sun Ho,KRX ; Heo Young Wook,KRX, Printed circuit board having epoxy barrier around a throughout slot and ball grid array semiconductor package.
상세보기
Chobot Ivan I. (Whitby NY CAX) Covert John A. (Binghamton NY) Haight Randy L. (Waverly NY) Mansfield Keith D. (New Milford PA) Miller Donald W. (Newark Valley NY) Neira Reinaldo A. (Endicott NY) Petr, Printed circuit board or card thermal mass design.
상세보기
Steffen Francis,FRX, Process for manufacturing a chip card micromodule with protection barriers.
상세보기
Wood Alan G. ; Akram Salman ; Farnworth Warren M., Process for manufacturing a semiconductor package with bi-substrate die.
상세보기
Wood Alan G. ; Farnworth Warren M., Process for packaging a semiconductor die using dicing and testing.
상세보기
Cobbley Chad, Process for providing electrical connection between a semiconductor die and a semiconductor die receiving member.
상세보기
Beddingfield Stanley C. ; Higgins ; III Leo M. ; Gentile John C., Process for underfilling a flip-chip semiconductor device.
상세보기
Farnworth Warren M. ; Wood Alan G., Process of making a glass semiconductor package.
상세보기
Wojnarowski Robert J. (Ballston Lake NY) Cole Herbert S. (Burnt Hills NY) Sitnik-Nieters Theresa A. (Scotia NY) Daum Wolfgang (Schenectady NY), Processing low dielectric constant materials for high speed electronics.
상세보기
McMillan ; II Richard Keith ; Jairazbhoy Vivek Amir ; Gordon Robert Joseph ; Garfinkel George Albert, Reflow soldering to mounting pads with vent channels to avoid skewing.
상세보기
Azuma Kousuke,JPX, Resin sealing mold die set with less resin remainder for semiconductor device.
상세보기
Tsuji Yukihiro (Kumamoto JPX), Resin-sealed semiconductor device.
상세보기
Sawaya Hiromichi (Kawasaki JPX) Ishigami Toshio (Kawasaki JPX), Resin-sealed type semiconductor device and method for manufacturing the same.
상세보기
Kanesaka Kenji,JPX, Sealed semiconductor device with positional deviation between upper and lower molds.
상세보기
Wilson Howard P. (Austin TX) Martin Fonzell D. J. (Austin TX), Self-opening vent hole in an overmolded semiconductor device.
상세보기
King Jerrold L. (Boise ID) Brooks Jerry M. (Caldwell ID), Semiconductor chip package.
상세보기
King Jerrold L. ; Nevill Leland R., Semiconductor chip package.
상세보기
Lee Kyu Jin,KRX ; Choi Wan Gyun,KRX, Semiconductor chip package using flexible circuit board with central opening.
상세보기
Tsuruzono Kimihiro,JPX, Semiconductor device.
상세보기
Yamaji Yasuhiro (Kawasaki JPX) Takahashi Kenji (Yokohama JPX) Hirata Seiichi (Yokosuka JPX) Sakurai Toshiharu (Yokohama JPX), Semiconductor device.
상세보기
Yamazaki Shunpei (Tokyo JPX), Semiconductor device having a film-covered packaged component.
상세보기
Romano\ Luigi (Monza ITX), Semiconductor device mounted in a highly flexible, segmented package, provided with heat sink.
상세보기
Akram Salman, Semiconductor devices having protective layers thereon through which contact pads are exposed and stereolithographic methods of fabricating such semiconductor devices.
상세보기
Larson Charles ; Fernandez John, Semiconductor lead frame and package with stiffened mounting paddle.
상세보기
Corisis David J., Semiconductor package.
상세보기
Sasaki Takaaki,JPX, Semiconductor package.
상세보기
Corisis David J., Semiconductor package having downset leadframe for reducing package bow.
상세보기
Corisis David J., Semiconductor package having downset leadframe for reducing package bow.
상세보기
Akram Salman, Semiconductor package having interlocking heat sinks and method of fabrication.
상세보기
Kinsman Larry D., Semiconductor package having metal foil die mounting plate.
상세보기
Moden Walter, Semiconductor package having stacked dice and leadframes and method of fabrication.
상세보기
Farnworth Warren M. ; Wood Alan G. ; Brooks Mike, Semiconductor package including flex circuit, interconnects and dense array external contacts.
상세보기
Brooks Mike ; Moden Walter L., Semiconductor package with heat sink and method of fabrication.
상세보기
Brooks Mike ; Moden Walter L., Semiconductor package with heat sink and method of fabrication.
상세보기
Takamichi Hiroshi,JPX ; Nakada Yoshikazu,JPX, Semiconductor package with improved moisture vapor relief function and method of fabricating the same.
상세보기
Farnworth Warren M. ; Hembree David R. ; Gochnour Derek ; Akram Salman ; Jacobson John O. ; Wark James M. ; Thummel Steven G., Semiconductor package with pre-fabricated cover and method of fabrication.
상세보기
Hembree David R. ; Akram Salman ; Gochnour Derek ; Farnworth Warren M., Semiconductor package with wire bond protective member.
상세보기
Akram Salman ; Wood Alan G. ; Farnworth Warren M., Single piece package for semiconductor die.
상세보기
Farnworth Warren M. ; Wood Alan G. ; Brooks Mike, Stacked semiconductor package and method of fabrication.
상세보기
Farnworth Warren M. ; Wood Alan G. ; Hembree David R. ; Akram Salman, Temporary package for semiconductor dice.
상세보기
Farnworth Warren M. ; Wood Alan G. ; Hembree David R. ; Akram Salman, Temporary package for semiconductor dice.
상세보기
Hembree David R. ; Farnworth Warren M ; Wood Alan G. ; Akram Salman, Temporary semiconductor package having dense array external contacts.
상세보기
Chamberlin Bruce J. ; Ferrill Mitchell G. ; Stutzman Randall J. ; Thiel George H., Thermal/electrical break for printed circuit boards.
상세보기
Kierse Oliver J.,IEX, Thermally efficient integrated circuit package.
상세보기
Jiang Tongbi ; Johnson Mark S., Thermally enhanced semiconductor package.
상세보기
Corisis David J., Transverse hybrid LOC package.
상세보기
Burns Carmen D., Ultra high density integrated circuit packages.
상세보기
Mitchell Craig S. ; Distefano Thomas H., Vacuum dispense apparatus for dispensing an encapsulant.
상세보기
Kinsman Larry D. ; Brooks Jerry M., Varied-thickness heat sink for integrated circuit (IC) packages and method of fabricating IC packages.
상세보기
Farnworth Warren M., Wafer level fabrication and assembly of chip scale packages.
상세보기
Akram Salman ; Wood Alan G., Wafer-level package and methods of fabricating.
상세보기
Lee Kyu Jin,KRX ; Jeong Do Soo,KRX ; Kim Jae June,KRX, Wire bond packages for semiconductor chips and related methods and assemblies.
상세보기

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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[미국특허] Method of Interconnecting substrates for electrical coupling of microelectronic components 원문보기

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[미국특허] Method of Interconnecting substrates for electrical coupling of microelectronic components 원문보기

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