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Semiconductor device having semiconductor element with copper pad mounted on wiring substrate and method for fabricating the same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/02
출원번호 US-0672783 (2000-09-18)
우선권정보 JP-0269272 (1999-09-22)
발명자 / 주소
  • Homma, Soichi
  • Miyata, Masahiro
  • Ezawa, Hirokazu
출원인 / 주소
  • Kabushiki Kaisha Toshiba
대리인 / 주소
    Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
인용정보 피인용 횟수 : 61  인용 특허 : 3

초록

After a copper diffusion preventing film 4 is formed on a copper pad 1 , a barrier metal including a titanium film 5 , a nickel film 6 , and a palladium film 7 is formed on the copper diffusion preventing film 4 . The copper diffusion preventing film formed on the copper pad suppresses diffusion of

대표청구항

1. A semiconductor device in which a semiconductor element having a copper pad is mounted on a wiring substrate, comprising:copper diffusion preventing film formed on the surface of said copper pad to prevent diffusion of copper;a metal film formed on the surface of said copper diffusion preventing

이 특허에 인용된 특허 (3)

  1. Costrini Gregory ; Goldblatt Ronald Dean ; Heidenreich ; III John Edward ; McDevitt Thomas Leddy, Method/structure for creating aluminum wirebound pad on copper BEOL.
  2. Hosomi Eiichi (Kawasaki JPX) Takubo Chiaki (Yokohama JPX) Tazawa Hiroshi (Ichikawa JPX) Miyamoto Ryouichi (Kawasaki JPX) Arai Takashi (Oita JPX) Shibasaki Koji (Kawasaki JPX), Semiconductor device comprising fine bump electrode having small side etch portion and stable characteristics.
  3. Mis Joseph Daniel ; Adema Gretchen Maerker ; Kellam Mark D. ; Rogers W. Boyd, Solder bump fabrication methods and structure including a titanium barrier layer.

이 특허를 인용한 특허 (61)

  1. Sun, Weimin; Zampardi, Jr., Peter J.; Shao, Hongxiao, Apparatus and methods for reducing impact of high RF loss plating.
  2. Sun, Weimin; Zampardi, Jr., Peter J.; Shao, Hongxiao, Apparatus and methods for reducing impact of high RF loss plating.
  3. Lee, Jin-Yuan; Lo, Hsin-Jung, Chip assembly with interconnection by metal bump.
  4. Lin, Mou-Shiung, Chip package and method for fabricating the same.
  5. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  6. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  7. Sakuyama,Seiki, Electronic component with bump electrodes, and manufacturing method thereof.
  8. Hosseini, Khalil; Stecher, Matthias, Electronic device and method for production.
  9. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.
  10. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.
  11. Lin, Mou-Shiung; Lo, Hsin-Jung; Chou, Chiu-Ming; Chou, Chien-Kang; Chen, Ke-Hung, Metal pad or metal bump over pad exposed by passivation layer.
  12. Wang, Tsing Chow, Method of forming low stress multi-layer metallurgical structures and high reliable lead free solder termination electrodes.
  13. Wang,Tsing Chow, Method of forming low stress multi-layer metallurgical structures and high reliable lead free solder termination electrodes.
  14. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  15. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  16. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  17. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  18. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  19. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  20. Sun, Weimin; Zampardi, Jr., Peter J.; Shao, Hongxiao, Methods to fabricate a radio frequency integrated circuit.
  21. Hada, Sayuri; Kawase, Kei; Matsumoto, Keiji; Orii, Yasumitsu; Toriyama, Kazushige, Mounting structure and mounting structure manufacturing method.
  22. Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Muzzy, Christopher D.; Sauter, Wolfgang, Ni plating of a BLM edge for Pb-free C4 undercut control.
  23. Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Muzzy, Christopher D.; Sauter, Wolfgang, Ni plating of a BLM edge for Pb-free C4 undercut control.
  24. Lin, Mou-Shiung; Lee, Jin-Yuan, Non-cyanide gold electroplating for fine-line gold traces and gold pads.
  25. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
  26. Ko, Tin Myint; Lehtola, Philip John; Ozalas, Matthew Thomas; Ripley, David Steven; Shao, Hongxiao; Zampardi, Jr., Peter J., Power amplifier modules including bipolar transistor with grading and related systems, devices, and methods.
  27. Ko, Tin Myint; Lehtola, Philip John; Ozalas, Matthew Thomas; Ripley, David Steven; Shao, Hongxiao; Zampardi, Jr., Peter J., Power amplifier modules including bipolar transistor with grading and related systems, devices, and methods.
  28. Chen, Howard E.; Guo, Yifan; Hoang, Dinhphuoc Vu; Janani, Mehran; Ko, Tin Myint; Lehtola, Philip John; LoBianco, Anthony James; Modi, Hardik Bhupendra; Nguyen, Hoang Mong; Ozalas, Matthew Thomas; Petty-Weeks, Sandra Louise; Read, Matthew Sean; Riege, Jens Albrecht; Ripley, David Steven; Shao, Hongxiao; Shen, Hong; Sun, Weimin; Sun, Hsiang-Chih; Welch, Patrick Lawrence; Zampardi, Jr., Peter J.; Zhang, Guohao, Power amplifier modules including related systems, devices, and methods.
  29. Zampardi, Jr., Peter J.; Sun, Hsiang-Chih; Shen, Hong; Janani, Mehran; Riege, Jens Albrecht, Power amplifier modules including tantalum nitride terminated through wafer via and related systems, devices, and methods.
  30. Modi, Hardik Bhupendra; Petty-Weeks, Sandra Louise; Shao, Hongxiao; Sun, Weimin; Zampardi, Jr., Peter J.; Zhang, Guohao, Power amplifier modules including wire bond pad and related systems, devices, and methods.
  31. Hoang, Dinhphuoc Vu; Modi, Hardik Bhupendra; Sun, Hsiang-Chih; Zampardi, Jr., Peter J.; Zhang, Guohao, Power amplifier modules with bifet and harmonic termination and related systems, devices, and methods.
  32. Modi, Hardik Bhupendra; Petty-Weeks, Sandra Louise; Shao, Hongxiao; Sun, Weimin; Zampardi, Jr., Peter J.; Zhang, Guohao, Power amplifier modules with bonding pads and related systems, devices, and methods.
  33. Sun, Weimin; Zampardi, Jr., Peter J.; Shao, Hongxiao; Zhang, Guohao; Modi, Hardik Bhupendra; Hoang, Dinhphuoc Vu, Power amplifier modules with harmonic termination circuit and related systems, devices, and methods.
  34. Zampardi, Jr., Peter J.; Sun, Hsiang-Chih; Petty-Weeks, Sandra Louise; Zhang, Guohao; Modi, Hardik Bhupendra, Power amplifier modules with power amplifier and transmission line and related systems, devices, and methods.
  35. Ishihara, Teruyuki; Ban, Hiroyuki; Mei, Haiying, Printed wiring board and method for manufacturing the same.
  36. Tomimori, Hiroaki; Aoki, Hidemitsu; Mikagi, Kaoru; Furuya, Akira; Tao, Tetsuya, Process for making a semiconductor device having a roughened surface.
  37. Sun, Weimin; Zampardi, Jr., Peter J.; Shao, Hongxiao, Radio frequency integrated circuit module.
  38. Lin, Mou-Shiung; Lee, Jin-Yuan, Semiconductor chip structure.
  39. Lin, Mou-Shiung; Yen, Huei-Mei; Lo, Hsin-Jung; Chou, Chiu-Ming; Chen, Ke-Hung, Semiconductor chip with a bonding pad having contact and test areas.
  40. Migita, Tatsuo; Ezawa, Hirokazu; Yamashita, Soichi; Nagamine, Koro; Miyata, Masahiro; Shiotsuki, Tatsuo; Muranishi, Kiyoshi, Semiconductor device and manufacturing method of semiconductor device.
  41. Lee, Dong-soo; Hwang, Eui-chul; Cho, Seong-ho; Lee, Myoung-jae; Lee, Sang-moon; Lee, Sung-hun; Uddin, Mohammad Rakib; Seo, David; Yang, Moon-seung; Hur, Ji-hyun, Semiconductor device and method of fabricating the same.
  42. Shigihara, Hiromi; Tsukamoto, Hiroshi; Yajima, Akira, Semiconductor integrated circuit device.
  43. Kaminaga, Toshiaki; Hayashi, Masahide; Ueyanagi, Katsumichi; Saito, Kazunori; Nishikawa, Mutsuo, Semiconductor pressure sensor.
  44. Lin, Mou-Shiung; Lin, Shih-Hsiung; Lo, Hsin-Jung; Chen, Ying-Chih; Chou, Chiu-Ming, Stacked chip package with redistribution lines.
  45. Lin, Mou-Shiung; Lin, Shih-Hsiung; Lo, Hsin-Jung; Chen, Ying-Chih; Chou, Chiu-Ming, Stacked chip package with redistribution lines.
  46. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  47. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  48. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  49. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  50. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  51. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  52. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  53. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  54. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  55. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  56. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
  57. Petty-Weeks, Sandra Louise; Zhang, Guohao; Modi, Hardik Bhupendra, Transmission line for high performance radio frequency applications.
  58. Sun, Weimin; Zampardi, Peter J.; Shao, Hongxiao, Wire bond pad system and method.
  59. Chou, Chiu-Ming; Lin, Shih-Hsiung; Lin, Mou-Shiung; Lo, Hsin-Jung, Wire bonding method for preventing polymer cracking.
  60. Lin, Mou-Shiung, Wirebond over post passivation thick metal.
  61. Gleixner,Robert J.; Danielson,Donald; Paluda,Patrick M.; Naik,Rajan, Wirebond structure and method to connect to a microelectronic die.
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