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Wire bonding process for copper-metallized integrated circuits 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0817696 (2001-03-23)
발명자 / 주소
  • Test, Howard R.
  • Amador, Gonzalo
  • Subido, Willmar E.
출원인 / 주소
  • Texas Instruments Incorporated
대리인 / 주소
    Brady, III Wade James
인용정보 피인용 횟수 : 108  인용 특허 : 29

초록

A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated circuits. The structure comprises a layer of barrier metal that resists copper diffusion, deposited on the non-oxidized copper surface in

대표청구항

1. A method for forming metallurgical connections between metal wires and bond pads positioned on integrated circuits having copper interconnecting metallization, comprising the steps of:depositing seed metal to activate the surface of said copper metallization of said bond pads;plating on said seed

이 특허에 인용된 특허 (29)

  1. Patel Sunil A. ; Chia Chok J. ; Desai Kishor V., Apparatus and method for improving ball joints in semiconductor packages.
  2. Iacovangelo Charles D. (Schenectady NY), Autocatalytic electroless gold plating composition.
  3. Andricacos Panayotis Constantinou ; Datta Madhav ; Horkans Wilma Jean ; Kang Sung Kwon ; Kwietniak Keith Thomas, Barrier layers for electroplated SnPb eutectic solder joints.
  4. Yamakawa Koji (Tokyo JPX) Iwase Nobuo (Kamakura JPX) Inaba Michihiko (Yokohama JPX), Bump and method of manufacturing the same.
  5. Iwabuchi Kaoru,JPX, Conductive bumps on pads for flip chip application.
  6. Jamin Ling ; Dave Charles Stepniak, Electroless Ni/Pd/Au metallization structure for copper interconnect substrate and method therefor.
  7. Mori Miki,JPX ; Kizaki Yukio,JPX ; Yasumoto Takaaki,JPX ; Yamakawa Koji,JPX ; Saito Masayuki,JPX ; Uchida Tatsuro,JPX ; Togasaki Takasi,JPX ; Yebisuya Takashi,JPX ; Murakami Taijun,JPX, Electronic circuit device.
  8. Nakano Hirotaka (Yokohama JPX) Yoshino Thunekazu (Kamakura JPX), Film carrier and bonding method using the film carrier.
  9. Nakano Hirotaka (Yokohama JPX) Yoshino Thunekazu (Kamakura JPX), Film carrier and bonding method using the film carrier.
  10. Ahmad Umar M. U. (Both of Hopewell Junction NY) Kumar Ananda H. (Both of Hopewell Junction NY) Perfecto Eric D. (Wappingers Falls NY) Prasad Chandrika (Wappingers Falls NY) Purushothaman Sampath (Yor, Interconnect structure having improved metallization.
  11. Krulik Gerald A. (El Toro CA) Mandich Nenad V. (Homewood IL), Low corrosivity catalyst for activation of copper for electroless nickel plating.
  12. Farnworth Warren M. ; Akram Salman, Method for fabricating a multi chip module with alignment member.
  13. Munroe Robert A. ; Greer Stuart E., Method for forming interconnect bumps on a semiconductor die.
  14. Jaynal Abedin Molla ; Owen Richard Fay, Method for processing a semiconductor substrate having a copper surface disposed thereon and structure formed.
  15. Bhatt Anilkumar Chinuprasad ; Bhatt Ashwinkumar C. ; Markovich Voya Rista ; Wilson William Earl ; Jones Gerald Walter, Method of preparing a substrate surface for conformal plating.
  16. Akram Salman ; Farnworth Warren M. ; Wood Alan G. ; Hembree David R., Method, apparatus and system for testing bumped semiconductor components.
  17. Farnworth Warren M. ; Akram Salman, Multi chip module including semiconductor wafer or dice, interconnect substrate, and alignment member.
  18. Akram Salman ; Farnworth Warren M., Non-oxidizing touch contact interconnect for semiconductor test systems and method of fabrication.
  19. Kaja Suryanarayana (Hopewell Junction NY) Mukherjee Shyama P. (Hopewell Junction NY) O\Sullivan Eugene J. (Upper Nyack NY) Paunovic Milan (Port Washington NY), Palladium sulfate solution for the selective seeding of the metal interconnections on polyimide dielectrics for electrol.
  20. Hirata Seiichi (Yokosuka JPX) Yoshida Akito (Chigasaki JPX), Semiconductor device having an opening and method of manufacturing the same.
  21. Hosomi Eiichi,JPX ; Tazawa Hiroshi,JPX ; Takubo Chiaki,JPX ; Shibasaki Koji,JPX, Semiconductor device using gold bumps and copper leads as bonding elements.
  22. Kondo Ichiharu (Nagoya JPX) Noritake Chikage (Ama-gun JPX) Watanabe Yusuke (Obu JPX), Semiconductor device with bump structure.
  23. Hosomi Eiichi,JPX ; Tazawa Hiroshi,JPX ; Takubo Chiaki,JPX ; Shibasaki Koji,JPX, Semiconductor device, method of fabricating the same and copper leads.
  24. Lopatin Sergey D. ; Iacoponi John A., Semiconductor metalization barrier and manufacturing method therefor.
  25. Farnworth Warren M. ; Wood Alan G. ; Brooks Mike, Semiconductor package including flex circuit, interconnects and dense array external contacts.
  26. Zakel Elke,DEX ; Aschenbrenner Rolf,DEX, Solder bump for flip chip assembly and method of its fabrication.
  27. Hembree David R. ; Farnworth Warren M ; Wood Alan G. ; Akram Salman, Temporary semiconductor package having dense array external contacts.
  28. Goodman Dale E. ; Hoffmeyer Mark K. ; Krabbenhoft Roger S., Universal surface finish for DCA, SMT and pad on pad interconnections.
  29. Budnaitis John J., Wafer level contact sheet and method of assembly.

이 특허를 인용한 특허 (108)

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