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Disconnecting a device on a cache line boundary in response to a write command 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/14
출원번호 US-0542157 (2000-04-04)
발명자 / 주소
  • Carlson, Jeff M.
  • Callison, Ryan A.
출원인 / 주소
  • Hewlett-Packard Development Company, L.P.
인용정보 피인용 횟수 : 36  인용 특허 : 8

초록

Efficient bus operations is provided by maintaining alignment with cache line boundaries in response to a write command. A write buffer in a bridge device receives data from any one of a multiple number of bus interfaces. Write buffer management is utilized to monitor on a continuous basis the amoun

대표청구항

1. A method for processing write commands from a device in a computer system, comprising the steps of:detecting a write command from a computer device, thereby initiating a write operation;receiving data in a buffer in response to the write command;monitoring the status of the buffer to determine th

이 특허에 인용된 특허 (8)

  1. Chard Gary F. ; Galloway William C. ; Callison Ryan A., Adaptive ahead FIFO with LRU replacement.
  2. Carlson Jeff M. (Cypress TX) Galloway William C. (Houston TX), Bridge circuit for preventing data incoherency by holding off propagation of data transfer completion interrupts until d.
  3. Thompson Mark J. (Spring TX) Schneider Randy D. (Spring TX), Computer network server backup with posted write cache disk controllers.
  4. Alexander Dennis J. (Spring TX) Callison Ryan A. (Spring TX) Perry Ralph S. (Houston TX), Disk drive controller with a posted write cache memory.
  5. Grieff Thomas W. ; Galloway William C. ; Carlson Jeff M., Locked exchange FIFO.
  6. Dobson William Gordon Keith, Serial port controller for preventing repetitive interrupt signals.
  7. Chen Edmund ; Hayek Claude ; Lotfi Jahan, System for allocating an integer unit of memory greater than a requested size and filling the extra space due to difference in sizes with extraneous data.
  8. Davis Barry R. ; Eskandari Nick G., Trigger points for performance optimization in bus-to-bus bridges.

이 특허를 인용한 특허 (36)

  1. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  2. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  3. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  4. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  7. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  8. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  9. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  10. Howard, Ric; Katragadda, Ramana V., Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture.
  11. Howard,Ric; Katragadda,Ramana V., Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture.
  12. Fujise, Shunichi; Fukui, Akitomo, Bridge and data processing method therefor.
  13. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  14. Burton, Scott E.; Coker, Kenny T.; Fallone, Robert M., Data storage device adjusting command rate profile based on operating mode.
  15. Perego, Richard E.; Ware, Frederick A., Early read after write operation memory device, system and method.
  16. Perego, Richard E; Ware, Frederick A, Early read after write operation memory device, system and method.
  17. Perego, Richard E; Ware, Frederick A, Early read after write operation memory device, system and method.
  18. Perego,Richard E.; Ware,Frederick A., Early read after write operation memory device, system and method.
  19. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  20. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  21. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  22. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  23. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  24. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  25. Perego,Richard E.; Ware,Frederick A., Memory device and system having a variable depth write buffer and preload method.
  26. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  27. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  28. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  29. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  30. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  31. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  32. Hu, Yong; Li, De-Jian; Gao, Gavin, Methods for processing multi-source data.
  33. Kryukov, Pavel I.; Shwartsman, Stanislav; Nuzman, Joseph; Titov, Alexandr, Sequential data writes to increase invalid to modified protocol occurrences in a computing system.
  34. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  35. Dinh, Peter H.; Barlow, Carl E.; Viglione, Joseph M.; Huynh, Sang; Tsai, Chun Sei, Throttled command completion time.
  36. Noguchi, Yasuo; Ogihara, Kazutaka; Tamura, Masahisa; Tsuchiya, Yoshihiro; Maruyama, Tetsutaro; Watanabe, Takashi; Kumano, Tatsuo; Oe, Kazuichi, Virtual disk management program, storage device management program, multinode storage system, and virtual disk managing method.
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