A controller (or controller chip) providing reduced power consumption without impacting performance is disclosed. The controller monitors activity of components within the controller which require access to a local memory, and then decreases a clocking frequency for a memory interface to the local m
A controller (or controller chip) providing reduced power consumption without impacting performance is disclosed. The controller monitors activity of components within the controller which require access to a local memory, and then decreases a clocking frequency for a memory interface to the local memory when the monitoring indicates that reduced amounts of activity are present. Following such a decrease in the clocking frequency, when increased amounts of activity are detected, the clocking frequency is increased for high performance operation. The controller thus tailors the clocking frequency for the memory interface in accordance with the amount of activity of these components that require access to the local memory so that overall less power is used by the controller yet the performance is essentially not hindered. In one embodiment, the controller is a graphics controller, as such controllers require access to local memories.
대표청구항▼
1. A method for managing power consumption of a graphics controller having an interface to a local memory, said method comprising:(a) determining a bandwidth load on the local memory, wherein said determining (a) includes at least: (a1) determining an amount of non-refresh activity for the graphics
1. A method for managing power consumption of a graphics controller having an interface to a local memory, said method comprising:(a) determining a bandwidth load on the local memory, wherein said determining (a) includes at least: (a1) determining an amount of non-refresh activity for the graphics controller, and (a2) determining the bandwidth load based on the amount of non-refresh activity; and(b) providing a clock to the interface, the clock having a frequency dependent upon the bandwidth load, and the interface providing access to the local memory at a rate determined by the frequency of the clock. 2. A method as recited in claim 1, wherein said method reduces power consumption by the graphics controller by reducing the frequency of the clock when the bandwidth load decreases. 3. A method as recited in claim 2, wherein following the prior reducing of the frequency of the clock, the frequency of the clock rapidly increases as the bandwidth load increases. 4. A method as recited in claim 1,wherein said method reduces power consumption by the graphics controller by reducing the frequency of the clock when the bandwidth load decreases, andwherein following the reducing of the frequency of the clock, the frequency of the clock rapidly increases as the bandwidth load increases. 5. A method as recited in claim 1,wherein the clock is also supplied to the local memory, andwherein said method reduces power consumption of the local memory and the interface to the local memory by reducing the frequency of the clock when the bandwidth load decreases. 6. A method for managing power consumption of a controller, a local memory being associated with the controller, said method comprising:receiving status information indicating local memory usage requirements for the local memory of the controller, the usage requirements pertaining to an amount of non-refresh activity within the controller;determining whether the usage requirements are below a threshold condition; andoperating the controller to interact with the local memory in accordance with a regular frequency clock when the usage requirements exceed the threshold condition or in accordance with a reduced frequency clock when the local memory usage requirements are below the threshold condition,wherein when the reduced frequency clock is used by the controller, power consumption of the controller is substantially lower as compared to the power consumption of the controller when the regular frequency clock is used. 7. A method as recited in claim 6, wherein the controller is a graphics controller. 8. A method as recited in claim 7, wherein the graphics controller performs a refresh operation with respect to a display device associated with the graphics controller, the refresh operation refreshes an image displayed on the display device by retrieving display information for the image from the local memory and thus represents a first usage amount for the local memory, andwherein the threshold condition pertains to a local memory usage amount that is greater than the first usage amount for the local memory. 9. A method as recited in claim 8, wherein the graphics controller includes at least one graphics functional unit, andwherein the usage requirements for the local memory of the graphics controller include the first usage amount and a usage amount for the at least one graphics functional unit when the at least one graphics functional unit is active. 10. A method as recited in claim 6,wherein the controller is a graphics controller,wherein the graphics controller includes at least one graphics functional unit, andwherein said method further comprises:providing the at least one graphics functional unit with a clock;determining when the at least one graphics functional unit is inactive; andstopping the clock provided to the at least one graphics functional unit when said determining determines that the at least one graphics functional unit is inactive. 11. A graphics controller for use with a computer system including a processor, a system bus and a display device, comprising:a system bus interface for coupling to the system bus of the computer system;a local memory;a local memory interface coupled to said local memory, said local memory interface controls access to said local memory;a display interface for coupling to the display device of the computer system;an arbitration unit coupled to said system bus interface, said local memory interface, and said display interface, said arbitration unit operates to arbitrate access to said local memory via said local memory interface, said arbitration unit providing a status signal pertaining to bandwidth load on said local memory; anda clock controller operatively connected to at least one of said local memory interface, said local memory and said arbitration unit, said clock controller producing a first clock based on the status signal, the first clock being for use by the at least one of said local memory interface and said local memory. 12. A graphics controller as recited in claim 11, wherein the first clock has a reduced frequency when said system bus interface does not require access to said local memory. 13. A graphics controller as recited in claim 12, wherein the reduced frequency of the first clock is at least fast enough to support a refresh operation of the display device. 14. A graphics controller as recited in claim 11,wherein said graphics controller further comprises:a graphics engine operatively connected to said arbitration unit, said graphics engine renders complex images to be displayed on the display device, andwherein said clock controller produces the first clock with a reduced frequency when said graphics engine does not require access to said local memory. 15. A graphics controller as recited in claim 11,wherein said graphics controller further comprises:a graphics engine operatively connected to said arbitration unit, said graphics engine renders complex images to be displayed on the display device, andwherein said clock controller produces the first clock with a reduced frequency when both said graphics engine and said system bus interface do not require access to said local memory. 16. A graphics controller as recited in claim 11,wherein the reduced frequency of the first clock is at least fast enough to support a refresh operation of the display device,wherein said graphics controller further comprises:a monitor operatively connected to said system bus interface, said graphics engine and said clock controller, said monitor operates to determine activity at the system bus interface and said graphic engine that requires usage of said local memory, andwherein said clock controller produces the clock with a frequency dependent on the activity determined by said monitor. 17. A graphics controller for use with a computer system including a processor, a system bus and a display device, comprising:a system bus interface for coupling to the system bus of the computer system;a local memory;a local memory interface coupled to said local memory, sa id local memory interface controls access to said local memory;a display interface for coupling to the display device of the computer system;a graphics engine operatively connected to said local memory interface, said graphics engine renders complex images to be displayed on the display device;means for monitoring activity of at least said system bus interface and said graphics engine to produce a memory access load indication; andmeans for producing a memory clock signal for use by at least one of said local memory interface and said local memory, the memory clock signal having a frequency that varies depending upon the memory access load indication, wherein the frequency is lower when the memory access load indication indicates a lack of or reduction in memory access activity. 18. A method as recited in claim 6, wherein said operating operates the controller to interact with the local memory in accordance w ith the reduced frequency clock only after the local memory usage requirements are determined to be below the threshold condition for at least a predetermined period of time.
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이 특허에 인용된 특허 (7)
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