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Power managed graphics controller 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/14
  • G06F-001/04
  • G06F-001/06
  • G06F-001/08
출원번호 US-0566651 (2000-05-08)
발명자 / 주소
  • Culbert, Michael F.
  • Howard, Brian D.
출원인 / 주소
  • Apple Computer, Inc.
대리인 / 주소
    Beyer Weaver & Thomas, LLP
인용정보 피인용 횟수 : 55  인용 특허 : 7

초록

A controller (or controller chip) providing reduced power consumption without impacting performance is disclosed. The controller monitors activity of components within the controller which require access to a local memory, and then decreases a clocking frequency for a memory interface to the local m

대표청구항

1. A method for managing power consumption of a graphics controller having an interface to a local memory, said method comprising:(a) determining a bandwidth load on the local memory, wherein said determining (a) includes at least: (a1) determining an amount of non-refresh activity for the graphics

이 특허에 인용된 특허 (7)

  1. Williams Ian Michael, Apparatus and method for dynamic central processing unit clock adjustment.
  2. Cross Randolph A., Circuits, systems and methods for interfacing processing circuitry with a memory.
  3. Lee Warren Atkinson, Demand-based processor clock frequency switching.
  4. Keith Sk Lee CA; David Sinclair CA, Dynamic memory clock control system and method.
  5. Cho Sung Soo ; Homayoun Nima, Method and apparatus for stopping a bus clock while there are no activities on a bus.
  6. Ian M. Williams ; Philip Cheng, Method and system for dynamic clock frequency adjustment for a graphics subsystem in a computer.
  7. Jun Dae-hyun,KRX ; Park Seung-ho,KRX, Technique for generating memory clock in video controller.

이 특허를 인용한 특허 (55)

  1. Bruno,John; Khodorkovsky,Oleksandr; Pang,Erwin; Phan,Gia, Adaptive temperature dependent feedback clock control system and method.
  2. Luong,Tien D.; Pang,Erwin, Apparatus and method for reducing power consumption in a graphics processing device.
  3. Fry, James, Apparatus and methods for control of a memory controller.
  4. Munguia, Peter R., Apparatus for adjusting a clock frequency of a variable speed bus.
  5. Abdalla, Karim M.; Hasslen, III, Robert J., Automatic functional block level clock-gating.
  6. Navale, Aditya; Samson, Eric C., Boosting graphics performance based on executing workload.
  7. Sadowski, Greg; Presant, Stephen David, Circuits and methods for providing adjustable power consumption.
  8. Du, Yun; Yu, Chun; Jiao, Guofang; Molloy, Stephen, Demand based power control in a graphics processing unit.
  9. Kardach, James P.; Williams, David; Bhowmik, Achintya K.; Cooper, Barnes, Display controller.
  10. Bounitch, Mikhail, Dynamic clock control circuit and method.
  11. Khodorkovsky, Oleksandr, Dynamic clock control circuit and method.
  12. Khodorkovsky,Oleksandr, Dynamic clock control circuit for graphics engine clock and memory clock and method.
  13. Samson, Eric C.; Navale, Aditya, Dynamic control of reduced voltage state of graphics controller component of memory controller.
  14. Samson, Eric C.; Navale, Aditya, Dynamic control of reduced voltage state of graphics controller component of memory controller.
  15. Samson, Eric C.; Navale, Aditya, Dynamic control of reduced voltage state of graphics controller component of memory controller.
  16. Samson, Eric C.; Navale, Aditya, Dynamic control of reduced voltage state of graphics controller component of memory controller.
  17. Samson, Eric C.; Navale, Aditya, Dynamic control of reduced voltage state of graphics controller component of memory controller.
  18. Bruno, John; Pang, Erwin, Dynamic memory clock switching circuit and method for adjusting power consumption.
  19. Pamley, Marc R.; Orro, Jose M.; Keown, Jr., William F.; Makley, Albert V., Dynamic memory voltage scaling for power management.
  20. Samson, Eric C.; Navale, Aditya, Dynamic power control for reduced voltage level of graphics controller component of memory controller based on its degree of idleness.
  21. Samson, Eric C.; Navale, Aditya, Dynamic power control for reduced voltage level of graphics controller component of memory controller based on its degree of idleness.
  22. Samson,Eric C.; Navale,Aditya, Dynamic power control for reducing voltage level of graphics controller component of memory controller based on its degree of idleness.
  23. Capps, Jr., Louis B.; Bell, Jr., Robert H.; Shapiro, Michael J., Dynamic processor reconfiguration for low power without reducing performance based on workload execution characteristics.
  24. Miwa, Masahiro; Naruse, Akira, Dynamically adjusting operating frequency of a arithemetic processing device for predetermined applications based on power consumption of the memory in real time.
  25. Miwa, Masahiro; Naruse, Akira, Dynamically adjusting operating frequency of a arithemetic processing device for predetermined applications based on power consumption of the memory in real time.
  26. Abdalla, Karim M.; Hasslen, III, Robert J., Functional block level clock-gating within a graphics processor.
  27. Avkarogullari, Gokhan; Law, Patrick Y.; Wyrzykowski, Michael J., GPU with dynamic performance adjustment.
  28. Jane, Jason P.; Schreyer, Richard W.; Swift, Michael J. E.; Avkarogullari, Gokhan; Semeria, Luc R.; Law, Patrick Y., Graphics hardware mode controls.
  29. Jane, Jason P.; Schreyer, Richard W.; Swift, Michael J. E.; Avkarogullari, Gokhan; Semeria, Luc R.; Law, Patrick Y., Graphics hardware mode controls.
  30. Schreyer, Richard W.; Jane, Jason P.; Swift, Michael J. E.; Avkarogullari, Gokhan; Semeria, Luc R., Graphics power control with efficient power usage during stop.
  31. Polzin, R. Stephen; Witek, Richard T.; Steinman, Maurice B., Integrating display controller into low power processor.
  32. Samson, Eric C., Managing power consumption by requesting an adjustment to an operating point of a processor.
  33. Dahan, Franck; Dubost, Gilles; Dubois, Sylvain, Memory controller idle mode.
  34. Jung, Jin-Su, Memory controller, memory system including the same and method of operating memory controller.
  35. David, Howard S.; Hanebutte, Ulf R.; Gorbatov, Eugene; Alexander, James W.; Sah, Suneeta, Memory power management via dynamic memory operation states.
  36. Samson,Eric C.; Navale,Aditya; Cline,Leslie E., Method and apparatus for dynamic DLL powerdown and memory self-refresh.
  37. Steinman, Maurice B.; Branover, Alexander J.; Krishnan, Guhan, Method for SOC performance and power optimization.
  38. Kawashima, Shinichi; Hitaka, Go; Tateshima, Hideharu, Portable terminal device.
  39. Munguia,Peter R., Power managed busses and arbitration.
  40. Law, Patrick Y.; Drebin, Robert A.; Cox, Keith; Ismail, James S., Power management for a graphics processing unit or other circuit.
  41. Law, Patrick Y.; Drebin, Robert A.; Cox, Keith; Ismail, James S., Power management for a graphics processing unit or other circuit.
  42. Law, Patrick Y.; Drebin, Robert A.; Cox, Keith; Ismail, James S., Power management for a graphics processing unit or other circuit.
  43. Jane, Jason P., Power management scheme that accumulates additional off time for device when no work is available and permits additional power consumption by device when awakened.
  44. Jane, Jason P., Power management scheme that accumulates additional off time for device when no work is available and permits additional power consumption by device when awakened.
  45. Jane, Jason P., Power management scheme that accumulates additional off time for device when off for an extended period and credits additional off time to power control feedback loop when awakened.
  46. Payne,Robert Edwin, Power management system.
  47. Samson, Eric C.; Navale, Aditya; Jensen, Richard; Sritanyaratana, Siripong; Cheng, Win S., Power/performance optimized memory controller considering processor power states.
  48. Elliott, John C.; Rinaldi, Brian A., Reducing storage system power consumption in a remote copy configuration.
  49. Elliott, John C.; Rinaldi, Brian A., Reducing storage system power consumption in a remote copy configuration.
  50. Lim, Sung-Ki, System and method for controlling display of mobile terminal.
  51. Branover, Alexander J.; Govindan, Madhu Saravana Sibi; Krishnan, Guhan; Mohapatra, Hemant R.; Lueck, Andrew W., System and method for determining a power estimate for an I/O controller based on monitored activity levels and adjusting power limit of processing units by comparing the power estimate with an assigned power limit for the I/O controller.
  52. Diard, Franck R., System and method for switching between graphical processing units.
  53. Diard, Franck R., System and method for switching between graphical processing units.
  54. Corlett, Barry; Conroy, David G; Millet, Timothy J; Culbert, Michael, Video rotation method and device.
  55. Takahashi, Satoshi; Yanagisawa, Ryogo; Iwata, Toru, Video signal processor capable of suppressing excessive heat generation, method using the same, display device and method using the same.
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