IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0078284
(2002-02-15)
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발명자
/ 주소 |
- Vanhaelemeersch, Serge
- Maex, Karen
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출원인 / 주소 |
- Interuniversitair Microelektronica Centrum (IMEC)
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대리인 / 주소 |
Knobbe Martens Olson & Bear LLP
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인용정보 |
피인용 횟수 :
1 인용 특허 :
9 |
초록
▼
This invention relates to Integrated Circuit (IC) processing and fabrication. A device and a method are provided for etching an opening in an insulating layer while depositing a barrier layer on the side walls of the opening without essentially depositing a barrier layer on the bottom of the opening
This invention relates to Integrated Circuit (IC) processing and fabrication. A device and a method are provided for etching an opening in an insulating layer while depositing a barrier layer on the side walls of the opening without essentially depositing a barrier layer on the bottom of the opening.
대표청구항
▼
1. A method for forming at least one opening in an insulating layer on a substrate while depositing a barrier layer on side walls of the opening without essentially depositing the barrier layer on a bottom of the opening, the method comprising the steps of:subjecting the substrate to a plasma, the p
1. A method for forming at least one opening in an insulating layer on a substrate while depositing a barrier layer on side walls of the opening without essentially depositing the barrier layer on a bottom of the opening, the method comprising the steps of:subjecting the substrate to a plasma, the plasma being generated in a gaseous mixture comprising at least three components, the components comprising a first component for depositing the metal barrier layer on at least the side walls of the opening, a second component for forming an opening in the insulating layer, and a third component for removing the barrier layer being formed on the bottom of the opening, wherein the first component is selected from the group consisting of 1-methyl silane, 2-methyl silane, 3-methyl silane, 4-methyl-silane, a mixture of SiH 4 and N 2 , a mixture of WF 6 and N 2 , and combinations thereof, wherein the second component is selected from the group consisting of N x O y , C x F y H x O u , N 2 /O 2 mixtures, N 2 /H 2 mixtures, O 2 , O 3 , NH 3 , CO, CO 2 , CH 4 , and combinations thereof, and wherein the third component comprises a chemical compound that forms a halogen ion or a halogen radical in the plasma;etching the insulating layer with the plasma; anddepositing the barrier layer on the side walls of the opening with the plasma. 2. A method as recited in claim 1, wherein the first component is selected from the group consisting of 3-methyl silane and 4-methyl-silane. 3. A method as recited in claim 1 wherein the second component is selected from the group consisting of N 2 /O 2 mixtures, N 2 /H 2 mixtures, and O 2 . 4. A method as recited in claim 1, wherein the third component is selected from the group consisting of CF 4 , CHF 3 , CH 2 F 2 , CHF 3 , and mixtures thereof. 5. A method as recited in claim 1, wherein the third component is selected from the group consisting of NF 3 , SF 6 , and mixtures thereof. 6. A method as recited in claim 1, wherein the gaseous mixture further comprises an inert gas selected from the group consisting of Ar, He, N 2 , and mixtures thereof. 7. A method as recited in claim 1, wherein the plasma is a continuous plasma. 8. A method as recited in claim 1, wherein the plasma is a pulsed plasma. 9. A method as recited in claim 1, wherein the barrier layer is a metal diffusion barrier layer. 10. A method as recited in claim 9, wherein the barrier layer comprises hydrogenated silicon carbide. 11. A method as recited in claim 1, wherein the insulating layer comprises a porous material. 12. A method as recited in claim 1, wherein the insulating layer is an organic containing insulating layer. 13. A method as recited in claim 1, wherein the insulating layer is an inorganic containing insulating layer. 14. A method as recited in claim 1, wherein the opening is a via hole, the via hole extending through the insulating layer to an underlying conductive layer or to an underlying barrier layer. 15. A method as recited in claim 1, further comprising the steps of:covering the insulating layer with a bilayer, the bilayer comprising a resist hard mask layer formed on the insulating layer and a resist layer formed on the hard mask layer; andpatterning the bilayer.
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