IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0855871
(2001-05-15)
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발명자
/ 주소 |
- Liu, Yi
- Hsu, Wei-Lien
- Gorishek, Frank
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출원인 / 주소 |
- Advanced Micro Devices, Inc.
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대리인 / 주소 |
Williams, Morgan & Amerson, P.C.
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인용정보 |
피인용 횟수 :
38 인용 특허 :
11 |
초록
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The invention, in a first aspect, is a method for mitigating edge effects in a decompressed video image. The method comprises first reads an N×N group of pixels defining a vertical edge between two blocks in a video frame row by row into N registers, wherein N is a predetermined number defining
The invention, in a first aspect, is a method for mitigating edge effects in a decompressed video image. The method comprises first reads an N×N group of pixels defining a vertical edge between two blocks in a video frame row by row into N registers, wherein N is a predetermined number defining the length of a filter. The content of the N registers is then transposed and then filtered in the filter. The filtered content of the N registers is then transposed and stored back from where it was read. In other aspects, the invention is a program storage device encoded with instructions that, when executed by a computer, perform such a method; a computer programmed to perform such a method; and a computing system capable of performing such a method.
대표청구항
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1. A method for mitigating edge effects in a decompressed video image, the method comprising:reading an N×N group of pixels defining a vertical edge between two blocks in a video frame row by row into N registers, wherein N is a predetermined number defining the length of a filter;transposing t
1. A method for mitigating edge effects in a decompressed video image, the method comprising:reading an N×N group of pixels defining a vertical edge between two blocks in a video frame row by row into N registers, wherein N is a predetermined number defining the length of a filter;transposing the content of the N registers;filtering the transposed content of the N registers in the filter;transposing the filtered content of the N registers; andstoring the transposed, filtered content of the registers back from whence it was read. 2. The method of claim 1, wherein the method is implemented in MMX or SSE2 instructions. 3. The method of claim 1, wherein reading the N×N group of pixels includes reading a 4×4 group of pixels. 4. The method of claim 3, wherein reading the 4×4 group of pixels defining the vertical edge between two blocks in the video frame row by row into N registers includes reading the pixels into 4 registers. 5. The method of claim 1, wherein reading then N×N group of pixels defining the vertical edge between two blocks in the video frame row by row into N registers includes reading the pixels into 4 registers. 6. The method of claim 1, wherein transposing the content of the N registers includes performing the following algorithm: 4 , MM 3 5 , MM 1 1 , MM 0 5 , MM 0 4 , MM 2 3 , MM 2 0 , MM 4 2 , MM 3 0 , MM 5 4 , MM 5 2 , MM 1 3 , MM 1 . 7. The method of claim 1, wherein filtering the transposed content of the N registers in the filter includes filtering the transposed content of the N registers in an H263v2 filter. 8. The method of claim 1, wherein transposing the filtered content of the N registers includes performing the following algorithm: 4 , MM 3 5 , MM 1 1 , MM 0 5 , MM 0 4 , MM 2 3 , MM 2 0 , MM 4 2 , MM 3 0 , MM 5 4 , MM 5 2 , MM 1 3 , MM 1 . 9. A program storage medium encoded with instructions that, when executed by a computer, perform a method for mitigating edge effects in a decompressed video image, the method comprising:reading an N×N group of pixels defining a vertical edge between two blocks in a video frame row by row into N registers, wherein N is a predetermined number defining the length of a filter;transposing the content of the N registers;filtering the transposed content of the N registers in the filter;transposing the filtered content of the N registers; andstoring the transposed, filtered content of the registers back from whence it was read. 10. The program storage medium of claim 9, wherein the encoded method is implemented in MMX or SSE2 instructions. 11. The program storage medium of claim 9, wherein reading the N×N group of pixels in the encoded method includes reading a 4×4 group of pixels. 12. The program storage medium of claim 11, wherein reading the 4×4 group of pixels defining the vertical edge between two blocks in the video frame row by row into N registers in the encoded method includes reading the pixels into 4 registers. 13. The program storage medium of claim 9, wherein reading then N×N group of pixels defining the vertical edge between two blocks in the video frame row by row into N registers in the encoded method includes reading the pixels into 4 registers. 14. The program storage medium of claim 9, wherein transposing the content of the N registers in the encoded method includes performing the following algorithm: 4 , MM 3 5 , MM 1 1 , MM 0 5 , MM 0 4 , MM 2 3 , MM 2 0 , MM 4 2 , MM 3 0 , MM 5 4 , MM 5 2 , MM 1 3 , MM 1 . 15. The program storage medium of claim 9, wherein filtering the transposed content of the N registers in the filter in the encoded method includes filtering the transposed content of the N registers in an H263v2 filter. 16. The program storage medium of claim 9, wherein transposing the filtered content of the N registers in the encoded method includes performing the following algorithm: 4 , MM 3 5 , MM 1 1 , MM 0 5 , MM 0 4 , MM 2 3 , MM 2 0 , MM 4 2 , MM 3 0 , MM 5 4 , MM 5 2 , MM 1 3 , MM 1 . 17. The program storage device of claim 9, wherein the program storage device is selected from the group consisting of a magnetic program storage device and an optical program storage device. 18. The program storage device of claim 17, wherein the selected program storage device is the magnetic program storage device and is a hard disk, a removable disk, or a RAM device. 19. The program storage device of claim 17, wherein the selected program storage device is the optical storage device and is a CD-ROM. 20. The program storage device of claim 9, wherein the program storage device is read-only or random access. 21. A computing device with a computer program embodied in a computer readable medium for performing a method of mitigating edge effects in a decompressed video image, the method comprising:reading an N×N group of pixels defining a vertical edge between two blocks in a video frame row by row into N registers, wherein N is a predetermined number defining the length of a filter;transposing the content of the N registers;filtering the transposed content of the N registers in the filter;transposing the filtered content of the N registers; andstoring the transposed, filtered content of the registers back from whence it was read. 22. The programmed computing device of claim 21, wherein the programmed method is implemented in MMX or SSE2 instructions. 23. The programmed computing device of claim 21, wherein reading the N×N group of pixels in the programmed method includes reading a 4×4 group of pixels. 24. The programmed computing device of claim 23, wherein reading the 4×4 group of pixels defining the vertical edge between two blocks in the video frame row by row into N registers in the programmed method includes reading the pixels into 4 registers. 25. The programmed computing device of claim 21, wherein reading then N×N group of pixels defining the vertical edge between two blocks in the video frame row by row into N registers in the programmed method includes reading the pixels into 4 registers. 26. The programmed computing device of claim 21, wherein transposing the content of the N registers in the programmed method includes performing the following algorithm: 4 , MM 3 5 , MM 1 1 , MM 0 5 , MM 0 4 , MM 2 3 , MM 2 0 , MM 4 2 , MM 3 0 , MM 5 4 , MM 5 2 , MM 1 3 , MM 1 . 27. The programmed computing device of claim 21, wherein filtering the transposed content of the N registers in the filter in the programmed method includes filtering the transposed content of the N registers in an H263v2 filter. 28. The programmed computing device of claim 21, wherein transposing the filtered content of the N registers in the programmed method includes performing the following algorithm: 4 , MM 3 5 , MM 1 1 , MM 0 5 , MM 0 4 , MM 2 3 , MM 2 0 , MM 4 2 , MM 3 0 , MM 5 4 , MM 5 2 , MM 1 3 , MM 1 . 29. The programmed computing device of claim 21, wherein the programmed computing device includes a data structure encoded on a program storage medium and reading the N×N group of pixels includes reading the N×N group of pixels from the data structure. 30. The programmed computing device of claim 29, wherein the program storage medium comprises a magnetic program storage device. 31. The programmed computing device of claim 30, wherein the magnetic program storage medium comprises a hard disk, a removable disk, or a RAM device. 32. The programmed computing device of claim 21, wherein the N registers are MMX registers. 33. A computing system, comprising:a processor;a first program storage device encoded with instructions that, when executed by the processor, perform a method for mitigating edge effects in a decompressed video image, the method comprising:reading an N×N group of pixels defining a vertical edge between two blocks in a video frame row by row into N registers, wherein N is a predetermined number defining the length of a filter;transposing the content of the N registers;filtering the transposed content of the N registers in the filter;transposing the filtered content of the N registers; andstoring the transposed, filtered content of the registers back from whence it was read;a second program storage device encoded with a data structure comprising video data from which the N×N group of pixels is read and to which the transposed, filtered content is stored. 34. The computing system of claim 33, wherein the encoded method is implemented in MMX or SSE2 instructions. 35. The computing system of claim 33, wherein reading the N×N group of pixels in the encoded method includes reading a 4×4 group of pixels. 36. The computing system of claim 35, wherein reading the 4×4 group of pixels defining the vertical edge between two blocks in the video frame row by row into N registers in the encoded method includes reading the pixels into 4 registers. 37. The computing system of claim 33, wherein reading then N×N group of pixels defining the vertical edge between two blocks in the video frame row by row into N registers in the encoded method includes reading the pixels into 4 registers. 38. The computing system of claim 33, wherein transposing the content of the N registers in the encoded method includes performing the following algorithm: 4 , MM 3 5 , MM 1 1 , MM 0 5 , MM 0 4 , MM 2 3 , MM 2 0 , MM 4 2 , MM 3 0 , MM 5 4 , MM 5 2 , MM 1 3 , MM 1 . 39. The computing system of claim 33, wherein filtering the transposed content of the N registers in the filter in the encoded method includes filtering the transposed content of the N registers in an H263v2 filter. 40. The computing system of claim 33, wherein transposing the filtered content of the N registers in the encoded method includes performing the following algorithm: 4 , MM 3 5 , MM 1 1 , MM 0 5 , MM 0 4 , MM 2 3 , MM 2 0 , MM 4 2 , MM 3 0 , MM 5 4 , MM 5 2 , MM 1 3 , MM 1 . 41. The computing system of claim 33, wherein the first program storage device is selected from the group consisting of a magnetic program storage device and an optical program storage device. 42. The computing system of claim 41, wherein the selected program storage device is the magnetic program storage device and is a hard disk, a removable disk, or a RAM device. 43. The computing system of claim 41, wherein the selected program storage device is the optical storage device and is a CD-ROM. 44. The computing system of claim 33, wherein the first program storage device is read-only or random access. 45. The computing system of claim 44, wherein the program storage medium comprises a magnetic program storage device. 46. The computing system of claim 45, wherein the magnetic program storage medium comprises a hard disk, a removable disk, or a RAM device. 47. The computing system of claim 33, wherein the N registers are MMX registers. 48. The computing system of claim 33, wherein the processor is selected from the group consisting of a microprocessor, a digital signal processor, and a graphics co-processor. 49. The computing system of claim 48, wherein the selected processor is the microprocessor and the microprocessor comprises an x86 compatible microprocessor with MMX capabilities. 50. The computing system of claim 48, wherein the x86 compatible microprocessor with MMX capabilities is the Athlon™ processor.
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