IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0945497
(2001-08-30)
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발명자
/ 주소 |
- Sandhu, Gurtej Singh
- Reinberg, Alan R.
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출원인 / 주소 |
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대리인 / 주소 |
Schwegman, Lundberg, Woessner & Kluth, P.A.
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인용정보 |
피인용 횟수 :
2 인용 특허 :
85 |
초록
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Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjac
Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.
대표청구항
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1. A semiconductor structure having a dielectric layer, comprising:a conductive container structure having a closed bottom and sidewalls extending upward from the closed bottom; anda dielectric cap on a top of the sidewalls, wherein the dielectric cap is adapted to remain on the top of the sidewalls
1. A semiconductor structure having a dielectric layer, comprising:a conductive container structure having a closed bottom and sidewalls extending upward from the closed bottom; anda dielectric cap on a top of the sidewalls, wherein the dielectric cap is adapted to remain on the top of the sidewalls and form part of the dielectric layer, wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides and silicon oxynitrides. 2. The semiconductor structure of claim 1, wherein the conductive container structure has a cylindrical shape. 3. The semiconductor structure of claim 1, wherein the closed bottom and sidewalls comprise at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon. 4. The semiconductor structure of claim 3, wherein the at least one silicon material is conductively doped. 5. A semiconductor structure having a dielectric layer, comprising:a conductive container structure having a closed bottom and sidewalls extending upward from the closed bottom, wherein the closed bottom and sidewalls comprise at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon; anda dielectric cap on a top of the sidewalls, wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides and silicon oxynitrides, and wherein the dielectric cap is adapted to remain on the top of the sidewalls and form part of the dielectric layer. 6. The semiconductor structure of claim 5, wherein the dielectric cap is annealed. 7. A semiconductor structure having a dielectric layer, comprising:a conductive container structure having sidewalls, wherein the conductive container structure comprises conductively-doped hemispherical grain polysilicon; anda dielectric cap on a top of the sidewalls, wherein the dielectric cap comprises silicon oxynitride, wherein the dielectric cap is adapted to remain on the top of the sidewalls and form part of the dielectric layer. 8. The semiconductor structure of claim 7, wherein the dielectric cap is annealed at approximately 600° C. to 1000° C. for approximately 10 to 20 seconds. 9. A semiconductor die, comprising:an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a container capacitor, the container capacitor comprising:a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom;a dielectric cap on a top of the sidewalls, wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides and silicon oxynitrides;a dielectric layer on the bottom plate and the dielectric cap; anda cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate. 10. The semiconductor die of claim 9, wherein the bottom plate has a cylindrical shape. 11. The semiconductor die of claim 9, wherein the bottom plate comprises at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon. 12. The semiconductor die of claim 11, wherein the at least one silicon material is conductively doped. 13. A semiconductor die, comprising:an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a container capacitor, the container capacitor comprising:a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom, wherein the bottom plate comprises at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon;a dielectric cap on a top of the sidewalls, wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides;a dielectric layer on the bottom plate and the dielectric cap; anda cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate. 14. A semiconductor die, comprising:an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a container capacitor, the container capacitor comprising:a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom, wherein the bottom plate comprises conductively-doped hemispherical grain polysilicon;a dielectric cap on a top of the sidewalls, wherein the dielectric cap comprises silicon oxynitride;a dielectric layer on the bottom plate and the dielectric cap; anda cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate. 15. The semiconductor die of claim 9, wherein the dielectric cap is annealed at approximately 600° C. to 1000° C. for approximately 10 to 20 seconds. 16. A memory device, comprising:an array of memory cells, wherein at least one memory cell has a container capacitor, the container capacitor comprising:a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom;a dielectric cap on a top of the sidewalls;a dielectric layer on the bottom plate and the dielectric cap; anda cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate;a row access circuit coupled to the array of memory cells;a column access circuit coupled to the array of memory cells; andan address decoder circuit coupled to the row access circuit and the column access circuit. 17. The memory device of claim 16, wherein the bottom plate has a cylindrical shape. 18. The memory device of claim 16, wherein the bottom plate comprises at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon. 19. The memory device of claim 18, wherein the at least one silicon material is conductively doped. 20. The memory device of claim 16, wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides. 21. A memory device, comprising:an array of memory cells, wherein at least one memory cell has a container capacitor, the container capacitor comprising:a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom, wherein the bottom plate comprises at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon;a dielectric cap on a top of the sidewalls, wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides;a dielectric layer on the bottom plate and the dielectric cap; anda cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate;a row access circuit coupled to the array of memory cells;a column access circuit coupled to the array of memory cells; andan address decoder circuit coupled to the row access circuit and the column access circuit. 22. A memory device, comprising:an array of memory cells, wherein at least one memory cell has a container capacitor, the container capacitor comprising:a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom, wherein the bottom plate comprises conductively-doped hemispherical grain polysilicon;a dielectric cap on a top of the sidewalls, wherein the dielectric cap comprises silicon oxynitride;a dielectric layer on the bottom plate and the diele ctric cap; anda cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate;a row access circuit coupled to the array of memory cells;a column access circuit coupled to the array of memory cells; andan address decoder circuit coupled to the row access circuit and the column access circuit. 23. The memory device of claim 22, wherein the dielectric cap is annealed at approximately 600° C. to 1000° C. for approximately 10 to 20 seconds. 24. A memory module, comprising:a support;a plurality of leads extending from the support;a command link coupled to at least one of the plurality of leads;a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; andat least one memory device contained on the support and coupled to the command link, wherein the at least one memory device comprises:an array of memory cells, wherein at least one memory cell has a container capacitor, the container capacitor comprising:a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom;a dielectric cap on a top of the sidewalls;a dielectric layer on the bottom plate and the dielectric cap; anda cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate;a row access circuit coupled to the array of memory cells;a column access circuit coupled to the array of memory cells; andan address decoder circuit coupled to the row access circuit and the column access circuit. 25. The memory module of claim 24, wherein the bottom plate has a cylindrical shape. 26. The memory module of claim 24, wherein the bottom plate comprises at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon. 27. The memory module of claim 26, wherein the at least one silicon material is conductively doped. 28. The memory module of claim 29, wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides. 29. A memory module, comprising:a support;a plurality of leads extending from the support;a command link coupled to at least one of the plurality of leads;a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; andat least one memory device contained on the support and coupled to the command link, wherein the at least one memory device comprises:an array of memory cells, wherein at least one memory cell has a container capacitor, the container capacitor comprising:a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom, wherein the bottom plate comprises at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon;a dielectric cap on a top of the sidewalls, wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides;a dielectric layer on the bottom plate and the dielectric cap; anda cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate;a row access circuit coupled to the array of memory cells;a column access circuit coupled to the array of memory cells; andan address decoder circuit coupled to the row access circuit and the column access circuit. 30. A memory module, comprising:a support;a plurality of leads extending from the support;a command link coupled to at least one of the plurality of leads;a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; andat least one memory device contained on the support and coupled to the command link, wherein the at least one memory device comprises:an array of memory cells, wherein at least one memory cell has a container capac itor, the container capacitor comprising:a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom, wherein the bottom plate comprises conductively-doped hemispherical grain polysilicon;a dielectric cap on a top of the sidewalls, wherein the dielectric cap comprises silicon oxynitride;a dielectric layer on the bottom plate and the dielectric cap; anda cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate;a row access circuit coupled to the array of memory cells;a column access circuit coupled to the array of memory cells; andan address decoder circuit coupled to the row access circuit and the column access circuit. 31. The memory module of claim 30, wherein the dielectric cap is annealed at approximately 600° C. to 1000° C. for approximately 10 to 20 seconds. 32. A memory system, comprising:a controller;a command link coupled to the controller;a data link coupled to the controller; anda memory device coupled to the command link and the data link, wherein the memory device comprises:an array of memory cells, wherein at least one memory cell has a container capacitor, the container capacitor comprising:a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom;a dielectric cap on a top of the sidewalls;a dielectric layer on the bottom plate and the dielectric cap; anda cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate;a row access circuit coupled to the array of memory cells;a column access circuit coupled to the array of memory cells; andan address decoder circuit coupled to the row access circuit and the column access circuit. 33. The memory system of claim 32, wherein the bottom plate has a cylindrical shape. 34. The memory system of claim 32, wherein the bottom plate comprises at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon. 35. The memory system of claim 34, wherein the at least one silicon material is conductively doped. 36. The memory system of claim 32, wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides. 37. A memory system, comprising:a controller;a command link coupled to the controller;a data link coupled to the controller; anda memory device coupled to the command link and the data link, wherein the memory device comprises:an array of memory cells, wherein at least one memory cell has a container capacitor, the container capacitor comprising:a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom, wherein the bottom plate comprises at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon;a dielectric cap on a top of the sidewalls, wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides;a dielectric layer on the bottom plate and the dielectric cap; anda cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate;a row access circuit coupled to the array of memory cells;a column access circuit coupled to the array of memory cells; andan address decoder circuit coupled to the row access circuit and the column access circuit. 38. A memory system, comprising:a controller;a command link coupled to the controller;a data link coupled to the controller; anda memory device coupled to the command link and the data link, wherein the memory device comprises:an array of memory cells, wherein at least one memory cell has a container capacitor, the container capacitor comprising:a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom, w herein the bottom plate comprises conductively-doped hemispherical grain polysilicon;a dielectric cap on a top of the sidewalls, wherein the dielectric cap comprises silicon oxynitride;a dielectric layer on the bottom plate and the dielectric cap; anda cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate;a row access circuit coupled to the array of memory cells;a column access circuit coupled to the array of memory cells; andan address decoder circuit coupled to the row access circuit and the column access circuit. 39. The memory system of claim 38, wherein the dielectric cap is annealed at approximately 600° C. to 1000° C. for approximately 10 to 20 seconds. 40. An electronic system, comprising:a processor; anda circuit module having a plurality of leads coupled to the processor, and further having a semiconductor die coupled to the plurality of leads, wherein the semiconductor die comprises:an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a container capacitor, the container capacitor comprising:a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom;a dielectric cap on a top of the sidewalls;a dielectric layer on the bottom plate and the dielectric cap; anda cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate. 41. The electronic system of claim 40, wherein the bottom plate has a cylindrical shape. 42. The electronic system of claim 40, wherein the bottom plate comprises at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon. 43. The electronic system of claim 42, wherein the at least one silicon material is conductively doped. 44. The electronic system of claim 40, wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides. 45. An electronic system, comprising:a processor; anda circuit module having a plurality of leads coupled to the processor, and further having a semiconductor die coupled to the plurality of leads, wherein the semiconductor die comprises:an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a container capacitor, the container capacitor comprising:a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom, wherein the bottom plate comprises at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon;a dielectric cap on a top of the sidewalls, wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides;a dielectric layer on the bottom plate and the dielectric cap; anda cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate. 46. An electronic system, comprising:a processor; anda circuit module having a plurality of leads coupled to the processor, and further having a semiconductor die coupled to the plurality of leads, wherein the semiconductor die comprises:an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a container capacitor, the container capacitor comprising:a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom, wherein the bottom plate comprises conductively-doped hemispherical grain polysilicon;a dielectric cap on a top of the sidewalls, wherein the dielectric cap comprises silicon oxynitride;a dielectric layer on the bottom plate and the dielectric cap; anda cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate. 47. The electronic system of claim 46, wherein the dielectric cap is annealed at approximately 600° C. to 1000° C. for approximately 10 to 20 seconds. 48. A semiconductor structure, comprising:a conductive container structure having a closed bottom and sidewalls extending upward from the closed bottom;an oxide dielectric cap on a top of the sidewalls; anda dielectric layer on the dielectric cap and the conductive container structure. 49. A semiconductor structure, comprising:a conductive container structure having a closed bottom and sidewalls extending upward from the closed bottom, wherein the closed bottom and sidewalls comprise at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon;a dielectric cap on a top of the sidewalls, wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of silicon oxides and silicon oxynitrides; anda dielectric layer on the dielectric cap and the conductive container structure. 50. A semiconductor structure, comprising:a conductive container structure having sidewalls, wherein the conductive container structure comprises conductively-doped hemispherical grain polysilicon;a dielectric cap on a top of the sidewalls, wherein the dielectric cap comprises silicon oxynitride; and a dielectric layer on the dielectric cap and the conductive container structure.
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