IPC분류정보
| 국가/구분 |
United States(US) Patent
등록
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| 국제특허분류(IPC7판) |
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| 출원번호 |
US-0779123
(2001-02-07)
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발명자
/ 주소 |
- Sethuraman, Anantha R.
- Seams, Christopher A.
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| 출원인 / 주소 |
- Cypress Semiconductor Corp.
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| 대리인 / 주소 |
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| 인용정보 |
피인용 횟수 :
4 인용 특허 :
102 |
초록
▼
The present invention advantageously provides a substantially planarized semiconductor topography and method for making the same by forming a plurality of dummy features in a dielectric layer between a relatively wide interconnect and a series of relatively narrow interconnect. According to an embod
The present invention advantageously provides a substantially planarized semiconductor topography and method for making the same by forming a plurality of dummy features in a dielectric layer between a relatively wide interconnect and a series of relatively narrow interconnect. According to an embodiment, a plurality of laterally spaced dummy trenches are first etched in the dielectric layer between a relatively wide trench and a series of relatively narrow trenches. The dummy trenches, the wide trench, and the narrow trenches are filled with a conductive material, e.g., a metal. The conductive material is deposited to a level spaced above the upper surface of the dielectric layer. The surface of the conductive material is then polished to a level substantially coplanar with that of the upper surface of the dielectric layer. Advantageously, the polish rate of the conductive material above the dummy trenches and the wide and narrow trenches is substantially uniform. In this manner, dummy conductors spaced apart by dielectric protrusions are formed exclusively in the dummy trenches, and interconnect are formed exclusively in the narrow and wide trenches. The topological surface of the resulting interconnect level is substantially void of surface disparity.
대표청구항
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1. A method, comprising:etching a plurality of laterally spaced dummy trenches into a dielectric layer between a first trench and a series of second trenches, wherein each of the second trenches is relatively narrow compared to the first trench; filling said trenches with a conductive material; and
1. A method, comprising:etching a plurality of laterally spaced dummy trenches into a dielectric layer between a first trench and a series of second trenches, wherein each of the second trenches is relatively narrow compared to the first trench; filling said trenches with a conductive material; and polishing said conductive material to form dummy conductors in said laterally spaced dummy trenches and interconnect in said series of second trenches and said first trench, wherein said polishing comprises applying a liquid substantailly free of particulate matter between an abrasive polishing surface and the conductive material. 2. The method of claim 1, wherein said conductive material comprises a metal selected from the group consisting of aluminum, copper, tungsten, molybdenum, tantalum, titanium, and alloys thereof.3. The method of claim 1, wherein said polishing said conductive material is performed at a substantially uniform polish rate above said laterally spaced dummy trenches and said series of relatively narrow second trenches and said first trench.4. The method of claim 1, wherein said polishing results in dummy dielectric protrusions between adjacent pairs of said laterally spaced dummy trenches, said dummy dielectric protrusions having first upper surfaces substantially coplanar with second upper surfaces of said dummy conductors.5. The method of claim 1, wherein said abrasive polishing surface comprises particles at least partially fixed into a polymer-based matrix, and wherein said particles comprise a material selected from the group consisting of cerium oxide, cerium dioxide, aluminum oxide, silicon dioxide, titanium oxide, chromium oxide, and zirconium oxide.6. The method of claim 1, wherein said polishing comprises placing a CMP slurry onto a polishing pad surface, and contacting said polishing pad surface with an upper surface of said conductive material while rotating said polishing pad surface relative to said upper surface.7. The method of claim 1, wherein said dummy conducts are substantially co-planar with said interconnect.8. The method of claim 1, wherein said polishing comprising applying a liquid consisting essentially of deionized water at a substantially neutral pH.9. A method comprising:etching a plurality of laterally spaced dummy trenches into a dielectric layer between a trench which is to receive a first interconnect feature and a series of trenches which are to receive a series of second interconnect features, wherein the first interconnect feature is relatively wide compared to each of the series of second interconnect features: filling said plurality of laterally spaced dummy trenches with a conductive material; and polishing said conductive material to form dummy conductors, wherein said polishing comprises applying a liquid substantially free of particulate matter between an abrasive polishing surface and the conductive material. 10. The method of claim 9, wherein said conductive material comprises a metal selected from the group consisting of aluminum, copper, tungsten, molybdenum, tantalum, titanium, and alloys thereof.11. The method of claim 9, wherein said polishing said conductive material is performed at a substantially uniform polish rate above said laterally spaced dummy trenches and said trench and said series of trenches.12. The method of claim 9, wherein said polishing results in dummy dielectric protrusion between adjacent pairs of said laterally spaced dummy trenches, said dummy dielectric protrusions having first upper surfaces substantially coplanar with second upper surfaces of said dummy conducts.13. The method of claim 9, wherein said abrasive polishing surface comprises particles at least partially fixed into a polymer-based matrix, and wherein said particles comprise a material selected from the group consisting of cerium oxide, cerium dioxide, aluminum oxide, silicon dioxide, titanium oxide, chromium oxide, and zirconium oxide.14. The method of claim 9, wherein said dummy conductors are substantially co-planar with said first interconnect feature and said series of second interconnect features.15. The method of claim 9, wherein said polishing comprising applying a liquid consisting essentially of deionized water at a substantially neutral pH.16. A substantially planar semiconductor topography, comprising:a plurality of laterally spaced dummy trenches in a dielectric layer, between a first trench and a series of second trenches, wherein each of the second trenches is relatively narrow compared to the first trench and wherein a lateral dimension of at least one of the laterally spaced dummy trenches is less than a lateral dimension of the first trench and greater than a lateral dimension of at least one of the series of second trenches; dummy conductors in said laterally spaced dummy trenches and electrically separate from electrically conductive features below said dummy conductors; and conductive lines in said series of second trenches and said first trench, wherein upper surfaces of said conductive lines are substantially coplanar with dummy conductor upper surfaces. 17. The substantially planar semiconductor topography of claim 16, further comprising dummy dielectric protrusions between adjacent pairs of said laterally spaced dummy trenches, said dummy dielectric protrusions having dummy dielectric upper surfaces substantially coplanar with said dummy conductor upper surfaces.18. The substantially planar semiconductor topography of claim 16,wherein said dummy conducts comprise a metal selected from the group consisting of a aluminum, copper, tungsten, molybdenum, tantalum, titanium, and alloys thereof.19. The substantially planar semiconductor topography of claim 16, wherein said conductive lines comprise a metal selected from the group consisting of aluminum, copper, tungsten, molybdenum, tantalum, titanium, and alloys thereof.20. The substantially planar semiconductor topography of claim 16, wherein lateral dimensions of the laterally spaced dummy trenches are between approximately 1 micron and approximately 5 microns.21. The substantially planar semiconductor topography of claim 16, wherein the lateral dimension of the first trench is greater than approximately 50 microns.22. The substantially planar semiconductor topography of claim 16, wherein the series of the second trenches comprise sub-micron lateral dimensions.
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