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Various methods, apparatuses and systems in which a memory uses a noise reduction circuit to sense groups of memory cells. The memory has a plurality of memory cells organized into groups of memory cells. The noise reduction circuit performs a sense operation on a first group of memory cells at the

Various methods, apparatuses and systems in which a memory uses a noise reduction circuit to sense groups of memory cells. The memory has a plurality of memory cells organized into groups of memory cells. The noise reduction circuit performs a sense operation on a first group of memory cells at the substantially the same time. The noise reduction circuit performs a sense operation on a second group of memory cells at substantially the same time. The noise reduction circuit has timing circuitry to sense the second group of memory cells after the sense of the first group initiates but prior to the completion of the sense operation on the first group of memory cells.

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1. An apparatus, comprising:an embedded memory having a plurality of memory cells arranged in a plurality of groups of memory cells, the plurality includes a first group of memory cells and a second group of memory cells; and a timing reference circuit coupled to the memory to direct a first sense o

1. An apparatus, comprising:an embedded memory having a plurality of memory cells arranged in a plurality of groups of memory cells, the plurality includes a first group of memory cells and a second group of memory cells; and a timing reference circuit coupled to the memory to direct a first sense operation on the first group of memory cells and a second sense operation on the second group of memory cells, the timing reference circuit to expose the first group of memory cells to a sense voltage timed so that a start of the second sense operation occurs for the second group of memory cells after the first sense operation is approximately complete. 2. The apparatus of claim 1, wherein the first group of memory cells includes electrically-alterable non-volatile memory cells.3. The apparatus of claim 1, wherein the first group of memory cells includes dynamic random access memory cells.4. The apparatus of claim 1, wherein the first group of memory cells includes static random access memory cells.5. The apparatus of a claim 1, wherein the timing reference circuit to generate a first control pulse having a falling edge and a second control pulse having a rising edge and approximately complete comprises less than a ten millisecond time elapse between the falling edge of the first control pulse of the first group memory cells and the rising edge of the second control pulse of the second group of memory cells.6. The apparatus of claim 1, wherein the timing reference circuit to generate a first control pulse having a rising edge and a second control pulse having a falling edge and approximately complete comprises less than a fifteen millisecond time elapse overlap occurs between the rising edge of the first control pulse of the first group memory cells and the falling edge of the second control pulse of the second group of memory cells.7. The apparatus of a claim 1, wherein the first group of memory cells consists of a single row of memory cells.8. The apparatus of a claim 2, wherein the first group of memory cells consists of a single column of memory cells.9. The apparatus of a claim 2, wherein all of the memory cells in the first group of non-volatile memory cells are sensed in parallel and loaded into corresponding volatile memory cells in parallel.10. The apparatus of a claim 2, wherein at least one or more of the electrically-alterable non-volatile memory cells data storage voltage is 400 millivolts or less.11. The apparatus of a claim 1, wherein the timing reference circuit includes:a first circuit to simulate the sense response time of all of the non-volatile memory cells in the first group; and a second circuit to simulate the load time of all of the volatile memory cells in the first group. 12. The apparatus of a claim 11, wherein the timing reference circuit further includes:a third circuit to generate a control signal to control the time period that the actual non-volatile memory cells in the first group are exposed to the sense voltage based upon receiving input from the first circuit and the second circuit. 13. The apparatus of a claim 1, wherein each group of memory cells communicates with its own timing reference circuit.14. A machine readable medium that stores data representing an embedded memory that includes:a plurality of electrically-alterable non-volatile memory cells arranged in a plurality of groups of memory cells, the plurality includes a first group of memory cells and a second group of memory cells; and a timing reference circuit coupled to the embedded memory to direct a first sense operation on the first group of memory cells and a second sense operation on the second group memory cells, the timing reference circuit to expose the first group of memory cells to a sense voltage timed so that a start of the second sense operation occurs for the second group of memory cells after the first sense operation is approximately complete. 15. The machine readable medium of claim 14 wherein the machine readable medium comprises a memory compiler to provide a design for one or more lithographic masks used in fabrication of the embedded memory.16. The machine readable medium of claim 15, wherein the design for the one or more lithographic masks are utilized during a standard Complementary Metal Oxide Semiconductor logic process employing equal to or less than one micron technology.17. An apparatus, comprising:a memory array having a non-volatile memory cooperating with a volatile memory to store and recall data; and a timing reference circuit to perform sense operations on two or more groups of memory cells in the memory array, the timing reference to initiate a first sense operation on a first group of memory cells when noise generation from a second sense operation on a second group of memory cells will not corrupt data being read from the first group of cells, wherein the timing reference circuit having timing circuitry to sense the second group of memory cells after the sense operation on the first group initiates but prior to the completion of the sense operation on the first group of memory cells. 18. The apparatus of claim 17, wherein the timing reference circuit performs the sense operation on the first group of memory cells at the substantially the same time by performing the sensing operation each memory cell in the first group of memory cells in parallel.19. The apparatus of claim 18, wherein the timing reference circuit has a first circuit to simulate the time it takes to sense all of the non-volatile cells in the first group of memory cells, and a second circuit to simulate the time it takes to load one or more volatile cells storing data from the first group of memory cells.20. The apparatus of claim 17, wherein the timing reference circuit contains a sense mimic circuit, a load mimic circuit, and a control signal circuit.21. The apparatus of claim 17, wherein the memory array comprises an embedded memory on a system on a chip.22. The apparatus of claim 17, further comprising:a group of non-volatile memory cells in the first group of memory cells; a sense circuit in the timing reference circuit, wherein the sense circuit to sense recall voltages using a Small Sensing Voltage to discern the recall data for all of the bits in the group of non-volatile memory cells in the non-volatile memory. 23. A machine readable medium that stores data representing the apparatus of claim 17.24. A machine readable medium that stores data representing the apparatus of claim 19.