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In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by an

In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region to form a nano-rod structure. Part of the nano-rod structure is then used as a gate channel. Preferably, a gate dielectric and a gate electrode both wrap around the nano-rod structure, with the gate dielectric being between the nano-rod structure and the gate electrode, to form a transistor device.

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1. A method of manufacturing a semiconductor device, comprising:providing a semiconductor structure comprising a semiconductor layer overlying an insulating material; patterning the semiconductor layer to form a source region, a channel region, and a drain region in the semiconductor layer, wherein

1. A method of manufacturing a semiconductor device, comprising:providing a semiconductor structure comprising a semiconductor layer overlying an insulating material; patterning the semiconductor layer to form a source region, a channel region, and a drain region in the semiconductor layer, wherein the channel region extends between the source region and the drain region; and rounding corners of the channel region by annealing. 2. The method of claim 1, wherein the annealing occurs in a reaction chamber having an environment therein including a gas selected from a group consisting of hydrogen, nitrogen, a mixed gas including hydrogen and argon, a mixed gas including hydrogen and nitrogen, and an inert gas.3. The method of claim 2, wherein the annealing environment is H2 gas at a pressure ranging from about 1.0×10?9 torr to about 800 torr.4. The method of claim 2, wherein the annealing environment is N2 gas at a pressure ranging from about 1.0×10?9 torr to about 800 torr.5. The method of claim 1, wherein the annealing occurs in a reaction chamber having an evacuated environment.6. The method of claim 5, wherein the annealing environment is a vacuum environment at a pressure ranging from about 1.0×10?10 torr to about 1.0×10?3 torr.7. The method of claim 1, wherein the annealing occurs in a reaction chamber having a temperature ranging from about 600° C. to about 1200° C. therein.8. The method of claim 1, wherein the annealing occurs at an anneal time ranging from about 1 second to about 2 hours.9. The method of claim 1, wherein the annealing is performed in a hydrogen gas (H2) environment at about 900° C. for about 2 minutes.10. The method of claim 1, further comprising:etching the insulating layer using an etch chemistry selective against etching the semiconductor layer, wherein the etching is performed long enough so that at least a segment of the channel region is suspended above a proximate portion of the insulating layer; forming a gate dielectric material on a surface of and about the rounded channel region; forming a gate electrode material on the gate dielectric and about the rounded channel region; and patterning the gate electrode material to form a gate electrode, the gate electrode comprising a gate wrap region that wraps around the rounded channel region and a gate contact region extending therefrom. 11. The method of claim 1, further comprising:doping exposed portions of the semiconductor layer. 12. A method of manufacturing a semiconductor nano-rod device, comprising:patterning a semiconductor layer to form a source region, a channel region, and a drain region in the semiconductor layer, wherein the channel region extends between the source region and the drain region; rounding corners of the channel region by annealing the channel region; etching the insulating layer using an etch chemistry selective against etching the semiconductor layer, wherein the etching is performed long enough so that at least a segment of the rounded channel region is suspended above a proximate portion of the insulating layer; forming a gate dielectric material on a surface of and about the rounded channel region; forming a gate electrode material on the gate dielectric and about the rounded channel region; and patterning the gate electrode material to form a gate electrode, the gate electrode comprising a gate wrap region that wraps around the rounded channel region and a gate contact region extending therefrom.