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Method of depositing barrier layer for metal gates 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/3205
  • H01L-021/4763
  • H01L-021/44
출원번호 US-0430811 (2003-05-05)
발명자 / 주소
  • Haukka, Suvi
  • Huotari, Hannu
출원인 / 주소
  • ASM International, NV
대리인 / 주소
    Knobbe, Martens, Olson &
인용정보 피인용 횟수 : 121  인용 특허 : 28

초록

A method of manufacturing a high performance MOS device and transistor gate stacks comprises forming a gate dielectric layer over a semiconductor substrate; forming a barrier layer over the gate dielectric layer by an ALD type process; and forming a gate electrode layer over the barrier layer. The m

대표청구항

1. A method of manufacturing a gate stack in an integrated circuit comprising:depositing a gate dielectric layer over a semiconductor substrate; depositing a barrier layer over the gate dielectric layer by an atomic layer deposition (ALD) type process essentially in the absence of direct plasma, rea

이 특허에 인용된 특허 (28)

  1. Vaartstra, Brian A., Aluminum-containing material and atomic layer deposition methods.
  2. Visokay, Mark Robert; Rotondaro, Antonio Luis Pacheco; Colombo, Luigi, Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing.
  3. Bai Gang ; Liang Chunlin, Complementary metal gates and a process for implementation.
  4. Bhattacharyya, Arup, Decoupling capacitor for high frequency noise immunity.
  5. Dimmler, Klaus; Gnadinger, Alfred P., Ferroelectric transistor for storing two data bits.
  6. Buchanan, Douglas A.; Callegari, Alessandro C.; Gribelyuk, Michael A.; Jamison, Paul C.; Neumayer, Deborah Ann, High mobility FETS using A1203 as a gate oxide.
  7. Fu, Tzy-Tzan; Lin, Kuan-Ting; Chou, Chao-Sheng, Limiting hydrogen ion diffusion using multiple layers of SiO2 and Si3N4.
  8. Chau Robert S. (Beaverton OR) Fraser David B. (Danville CA) Cadien Kenneth C. (Portland OR) Raghavan Gopal (Mountain View CA) Yau Leopoldo D. (Portland OR), MOS transistor having a composite gate electrode and method of fabrication.
  9. Yu Bin, MOS transistor with dual metal gate structure.
  10. Park, Dae-Gyu; Jang, Se-Aug; Lee, Jeong-Youb; Cho, Hung-Jae; Kim, Jung-Ho, Method for forming aluminum oxide as a gate dielectric.
  11. Liang Chunlin ; Bai Gang, Method for making a complementary metal gate electrode technology.
  12. Sergey D. Lopatin ; Carl Galewski ; Takeshi T. N. Nogami JP, Method of copper interconnect formation using atomic layer copper deposition.
  13. Schinella, Richard, Method of forming SiGe gate electrode.
  14. Ma, Yanjun; Ono, Yoshi, Method of forming a multilayer dielectric stack.
  15. Wilk Glen D. ; Summerfelt Scott R., Method of forming dual metal gate structures or CMOS devices.
  16. Chau Robert S. ; Fraser David B. ; Cadien Kenneth C. ; Raghavan Gopal ; Yau Leopoldo D., Method of frabricating a MOS transistor having a composite gate electrode.
  17. Pekka J. Soininen FI; Kai-Erik Elers FI; Suvi Haukka FI, Method of growing electrical conductors by reducing metal oxide film with organic compound containing -OH, -CHO, or -COOH.
  18. Cha, Tae Ho; Jang, Se Aug; Kim, Tae Kyun; Park, Dea Gyu; Yeo, In Seok; Park, Jin Won, Method of manufacturing a transistor in a semiconductor device.
  19. Park, Dae Gyu; Cha, Tae Ho; Jang, Se Aug; Cho, Heung Jae; Kim, Tae Kyun; Lim, Kwan Yong; Yeo, In Seok; Park, Jin Won, Method of manufacturing semiconductor devices with titanium aluminum nitride work function.
  20. Wenhe Lin SG; Mei-Sheng Zhou SG; Kin Leong Pey SG; Simon Chooi SG, Methods to form dual metal gates by incorporating metals and their conductive oxides.
  21. Yanjun Ma ; Yoshi Ono, Multilayer dielectric stack and method.
  22. Senzaki, Yoshihide, Multilayer high κ dielectric films.
  23. Ngai, Tat; Nguyen, Bich-Yen; Kaushik, Vidya S.; Schaeffer, Jamie K., Semiconductor device and a method therefor.
  24. Chabal, Yves Jean; Green, Martin Laurence; Wilk, Glen David, Semiconductor device having a high-K gate dielectric and method of manufacture thereof.
  25. Isik C. Kizilyalli ; Ranbir Singh ; Lori Stirling, Semiconductor device having a metal gate with a work function compatible with a semiconductor device.
  26. Gardner Mark I. ; Fulford H. Jim ; May Charles E. ; Hause Fred ; Kwong Dim-Lee, Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof.
  27. Hegde, Rama I.; Mogab, Joe; Tobin, Philip J.; Tseng, Hsing H.; Liu, Chun-Li; Borucki, Leonard J.; Merchant, Tushar P.; Hobbs, Christopher C.; Gilmer, David C., Transistor with layered high-K gate dielectric and method therefor.
  28. Jun-Fei Zheng ; Brian Doyle ; Gang Bai ; Chunlin Liang, Work function tuning for MOSFET gate electrodes.

이 특허를 인용한 특허 (121)

  1. Ootsuka, Fumio, 3D stacked multilayer semiconductor memory using doped select transistor channel.
  2. Wang, Chang-Gong; Shero, Eric; Wilk, Glen, ALD of metal silicate films.
  3. Wang, Chang-Gong; Shero, Eric; Wilk, Glen, ALD of metal silicate films.
  4. Marquardt, David; Shugrue, John, Apparatus and method for calculating a wafer position in a processing chamber under process conditions.
  5. Oosterlaken, Theodorus; de Ridder, Chris; Jdira, Lucian, Apparatus and method for manufacturing a semiconductor device.
  6. Kamiya, Tatsuo, Apparatus and method for transporting wafers between wafer carrier and process tool under vacuum.
  7. den Hartog Besselink, Edwin; Garssen, Adriaan; Dirkmaat, Marco, Cassette holder assembly for a substrate cassette and holding member for use in such assembly.
  8. Halpin, Michael; Shero, Eric; White, Carl; Alokozai, Fred; Winkler, Jerry; Dunn, Todd, Chamber sealing member.
  9. Zaitsu, Masaru; Fukazawa, Atsuki; Fukuda, Hideaki, Continuous process incorporating atomic layer etching.
  10. Raisanen, Petri; Shero, Eric; Haukka, Suvi; Milligan, Robert Brennan; Givens, Michael Eugene, Deposition of metal borides.
  11. Zhu, Chiyu; Shrestha, Kiran; Haukka, Suvi, Deposition of metal borides.
  12. Okura, Seiji; Suemori, Hidemi; Pore, Viljami J., Deposition of titanium nanolaminates for use in integrated circuit fabrication.
  13. Yednak, III, Andrew M.; Dunn, Todd; White, Carl; Manasco, Michael, Deposition valve assembly and method of heating the same.
  14. Wang, Chang-Gong; Shero, Eric, Doping with ALD technology.
  15. Milligan, Robert Brennan, Formation of boron-doped titanium metal films with high work function.
  16. Hawkins, Mark; Halleck, Bradley Leonard; Kirschenheiter, Tom; Hossa, Benjamin; Pottebaum, Clay; Miskys, Claudio, Gas distribution system, reactor including the system, and methods of using the same.
  17. Yoon, Jaeman; Kim, Yungi; Seo, Hyeoungwon; Lee, Kangyoon, Gate electrode structure.
  18. Kher, Shreyas, Hardware set for growth of high k and capping material films.
  19. Yednak, III, Andrew M.; Pettinger, Jr., Frederick L., Heater jacket for a fluid line.
  20. Im,Ki Vin; Park,Ki Yeon; Yeo,Jae Hyun; Park,In Sung; Lee,Seung Hwan; Kim,Young Sun; Kim,Sung Tae, High performance MIS capacitor with HfOdielectric.
  21. Chan, Meng-Hsuan; Lee, Wei-Yang; Lee, Da-Yuan; Hsu, Kuang-Yuan, High temperature anneal for stress modulation.
  22. Song, Zhe; Sigman, Jennifer K., Interfacial materials for use in semiconductor structures and related methods.
  23. Shugrue, John; Moen, Ron, Lockout tagout for semiconductor vacuum valve.
  24. Li, Wei Min, Low resistivity metal carbonitride thin film deposition by atomic layer deposition.
  25. Cabral, Jr., Cyril; Detavernier, Christophe; Jammy, Rajarao; Saenger, Katherine L., Metal carbide gate structure and method of fabrication.
  26. Jung, Sung-Hoon, Metal oxide protective layer for a semiconductor device.
  27. Pore, Viljami, Method and apparatus for filling a gap.
  28. Pore, Viljami; Knaepen, Werner; Jongbloed, Bert; Pierreux, Dieter; Van Aerde, Steven R. A.; Haukka, Suvi; Fukuzawa, Atsuki; Fukuda, Hideaki, Method and apparatus for filling a gap.
  29. Pore, Viljami; Knaepen, Werner; Jongbloed, Bert; Pierreux, Dieter; Van Der Star, Gido; Suzuki, Toshiya, Method and apparatus for filling a gap.
  30. Doris, Bruce B.; Cheng, Kangguo; Khakifirooz, Ali; Kerber, Pranita, Method and structure for forming high-K/metal gate extremely thin semiconductor on insulator device.
  31. Doris, Bruce B.; Cheng, Kangguo; Khakifirooz, Ali; Kulkarni, Pranita, Method and structure for forming high-K/metal gate extremely thin semiconductor on insulator device.
  32. Tolle, John; Hill, Eric; Winkler, Jereld Lee, Method and system for in situ formation of gas-phase compounds.
  33. Jung, Sung-Hoon; Raisanen, Petri; Liu, Eric Jen Cheng; Schmotzer, Mike, Method and system to reduce outgassing in a reaction chamber.
  34. Winkler, Jereld Lee, Method and systems for in-situ formation of intermediate reactive species.
  35. Sunil, Wickramanayaka; Kosuda, Motomu; Yamada, Naoki; Kitano, Naomu, Method for depositing a metal gate on a high-k dielectric film.
  36. Suemori, Hidemi, Method for depositing dielectric film in trenches by PEALD.
  37. Kang, DongSeok, Method for depositing thin film.
  38. Hendriks, Menso; Knapp, Martin; Haukka, Suvi, Method for depositing thin films by mixed pulsed CVD and ALD.
  39. Takamure, Noboru; Okabe, Tatsuhiro, Method for forming Ti-containing film by PEALD using TDMAT or TDEAT.
  40. Shiba, Eiichiro, Method for forming aluminum nitride-based film by PEALD.
  41. Winkler, Jereld Lee, Method for forming conformal carbon films, structures conformal carbon film, and system of forming same.
  42. Fukazawa, Atsuki, Method for forming conformal nitrided, oxidized, or carbonized dielectric film by atomic layer deposition.
  43. Fukazawa, Atsuki; Fukuda, Hideaki; Takamure, Noboru; Zaitsu, Masaru, Method for forming dielectric film in trenches by PEALD using H-containing gas.
  44. Kimura, Yosuke; de Roest, David, Method for forming film having low resistance and shallow junction depth.
  45. Murray, Conal E.; Yang, Chih-Chao, Method for forming improved liner layer and semiconductor device including the same.
  46. Ishikawa, Dai; Fukazawa, Atsuki, Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches.
  47. Namba, Kunitoshi, Method for forming silicon oxide cap layer for solid state diffusion process.
  48. Shiba, Eiichiro, Method for performing uniform processing in gas system-sharing multiple reaction chambers.
  49. Yamagishi, Takayuki; Suwada, Masaei; Tanaka, Hiroyuki, Method for positioning wafers in multiple wafer transport.
  50. Kato, Richika; Nakano, Ryu, Method for protecting layer by forming hydrocarbon-based extremely thin film.
  51. Kato, Richika; Okuro, Seiji; Namba, Kunitoshi; Nonaka, Yuya; Nakano, Akinori, Method for protecting layer by forming hydrocarbon-based extremely thin film.
  52. Haukka, Suvi; Shero, Eric James; Alokozai, Fred; Li, Dong; Winkler, Jereld Lee; Chen, Xichong, Method for treatment of deposition reactor.
  53. Zaitsu, Masaru, Method of atomic layer etching using functional group-containing fluorocarbon.
  54. Wu,Chih Ning; Lee,Charlie C J; Liao,Kuan Yang, Method of cleaning wafer and method of manufacturing gate structure.
  55. Zaitsu, Masaru; Kobayashi, Nobuyoshi; Kobayashi, Akiko; Hori, Masaru; Kondo, Hiroki; Tsutsumi, Takayoshi, Method of cyclic dry etching using etchant film.
  56. Knaepen, Werner; Maes, Jan Willem; Jongbloed, Bert; Kachel, Krzysztof Kamil; Pierreux, Dieter; De Roest, David Kurt, Method of forming a structure on a substrate.
  57. Lee, Choong Man; Yoo, Yong Min; Kim, Young Jae; Chun, Seung Ju; Kim, Sun Ja, Method of forming metal interconnection and method of fabricating semiconductor apparatus using the method.
  58. Chun, Seung Ju; Yoo, Yong Min; Choi, Jong Wan; Kim, Young Jae; Kim, Sun Ja; Lim, Wan Gyu; Min, Yoon Ki; Lee, Hae Jin; Yoo, Tae Hee, Method of processing a substrate and a device manufactured by using the method.
  59. Haukka, Suvi; Huotari, Hannu, Method of producing thin films.
  60. Kohen, David; Profijt, Harald Benjamin, Methods for depositing a doped germanium tin semiconductor and related semiconductor device structures.
  61. Raisanen, Petri; Givens, Michael Eugene, Methods for forming a transition metal nitride film on a substrate by atomic layer deposition and related semiconductor device structures.
  62. Currie,Matthew T., Methods for forming dielectrics and metal electrodes.
  63. Tolle, John, Methods of forming films including germanium tin and structures and devices including the films.
  64. Margetis, Joe; Tolle, John, Methods of forming highly p-type doped germanium tin films and structures and devices including the films.
  65. Margetis, Joe; Tolle, John, Methods of forming silicon germanium tin films and structures and devices including the films.
  66. Choi,Kisik; Alshareef,Husam; Majhi,Prashant, Methods of modulating the work functions of film layers.
  67. Ando, Takashi; Dasgupta, Aritra; Kwon, Unoh; Polvino, Sean M., Multi-layer work function metal replacement gate.
  68. Ando, Takashi; Dasgupta, Aritra; Kwon, Unoh; Polvino, Sean M., Multi-layer work function metal replacement gate.
  69. Zhu, Chiyu; Asikainen, Timo; Milligan, Robert Brennan, NbMC layers.
  70. Milligan, Robert Brennan; Alokozai, Fred, Phase-stabilized thin films, structures and devices including the thin films, and methods of forming same.
  71. Milligan, Robert B.; Li, Dong; Marcus, Steven, Plasma-enhanced atomic layer deposition of conductive material over dielectric layers.
  72. Milligan, Robert B.; Li, Doug; Marcus, Steven, Plasma-enhanced atomic layers deposition of conductive material over dielectric layers.
  73. Doh,Seok Joo; Jung,Hyung suk; Lee,Nae in; Lee,Jong ho; Kim,Yun seok, Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices.
  74. Van Aerde, Steven R. A.; de Blank, Rene, Prevention of oxidation of substrate surfaces in process chambers.
  75. Pettinger, Fred; White, Carl; Marquardt, Dave; Ibrani, Sokol; Shero, Eric; Dunn, Todd; Fondurulia, Kyle; Halpin, Mike, Process feed management for semiconductor substrate processing.
  76. Machkaoutsan, Vladimir; Maes, Jan Willem; Xie, Qi, Process for depositing electrode with high effective work function.
  77. Pore, Viljami J.; Okura, Seiji; Suemori, Hidemi, Process for deposition of titanium oxynitride for use in integrated circuit fabrication.
  78. Pore, Viljami J.; Okura, Seiji; Suemori, Hidemi, Process for deposition of titanium oxynitride for use in integrated circuit fabrication.
  79. Margetis, Joe; Tolle, John; Bartlett, Gregory; Bhargava, Nupur, Process for forming a film on a substrate using multi-port injection assemblies.
  80. Putkonen, Matti, Process for producing zirconium oxide thin films.
  81. Putkonen, Matti, Process for producing zirconium oxide thin films.
  82. Alokozai, Fred; Milligan, Robert Brennan, Process gas management for an inductively-coupled plasma deposition reactor.
  83. Alokozai, Fred; Milligan, Robert Brennan, Process gas management for an inductively-coupled plasma deposition reactor.
  84. Yao, Liang-Gi; Wang, Ming-Fang; Chen, Shih-Chang; Liang, Mong-Song, Process to make high-K transistor dielectrics.
  85. Yao, Liang-Gi; Wang, Ming-Fang; Chen, Shih-Chang; Liang, Mong-Song, Process to make high-K transistor dielectrics.
  86. Yoshimi, Tatsuya; de Blank, Rene; Noiray, Jerome, Protection of conductors from oxidation in deposition chambers.
  87. Winkler, Jereld Lee, Pulsed remote plasma method and system.
  88. Shero, Eric; Halpin, Michael; Winkler, Jerry, Radiation shielding for a substrate holder.
  89. Zhu, Chiyu, Selective film deposition method to form air gaps.
  90. Noiray, Jerome; Granneman, Ernst H. A., Selective removal of oxygen from metal-containing materials.
  91. Kimizuka, Naohiko; Imai, Kiyotaka; Masuoka, Yuri; Iwamoto, Toshiyuki, Semiconductor device.
  92. Kim, Young Jae; Choi, Seung Woo; Yoo, Yong Min, Semiconductor device and manufacturing method thereof.
  93. Kim, Dae Young, Semiconductor device and method for fabricating the same.
  94. Raisanen, Petri; Givens, Michael; Verghese, Mohith, Semiconductor device dielectric interface layer.
  95. Pae, Sangwoo; Maiz, Jose; Brask, Justin; Dewey, Gilbert; Kavalieros, Jack; Chau, Robert; Datta, Suman, Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer.
  96. Moon, Bum Ki; Shum, Danny Pak-Chum; Chae, Moosung, Semiconductor devices and methods of manufacture thereof.
  97. Moon, Bum Ki; Shum, Danny Pak-Chum; Chae, Moosung, Semiconductor devices and methods of manufacture thereof.
  98. Hsiao, Yu-Tung; Lin, Chien-Liang; Wang, Yu-Ren, Semiconductor process.
  99. Shero, Eric; Verghese, Mohith E.; White, Carl L.; Terhorst, Herbert; Maurice, Dan, Semiconductor processing reactor and components thereof.
  100. Milligan, Robert Brennan; Alokozai, Fred, Semiconductor reaction chamber with plasma capabilities.
  101. Xie, Qi; Machkaoutsan, Vladimir; Maes, Jan Willem, Semiconductor structure and device and methods of forming same using selective epitaxial process.
  102. Lo, Yi-Jen; Chiu, Yu-Shan; Su, Kuo-Hui; Lin, Chiang-Hung, Semiconductor structure and method for making the same.
  103. Arai, Izumi, Single-and dual-chamber module-attachable wafer-handling chamber.
  104. Xie, Qi; de Roest, David; Woodruff, Jacob; Givens, Michael Eugene; Maes, Jan Willem; Blanquart, Timothee, Source/drain performance through conformal solid state doping.
  105. Weeks, Keith Doran, Structures and devices including a tensile-stressed silicon arsenic layer and methods of forming same.
  106. Tolle, John, Structures and devices including germanium-tin films and methods of forming same.
  107. Lai, Chao-Sung; Yu, Jau-Song; Chang, Yu-Sun; Yang, Po-Lung; Lu, Tseng-Fu; Lin, Yi-Ting; Chuang, Wen-Yu; Yu, Ting-Chun; Wang, I-Shun; Chen, Jyh-Ping; Chien, Chou, Surface treatment method by using the NH3 plasma treatment to modify the sensing thin-film.
  108. Jeong, Sang Jin; Han, Jeung Hoon; Choi, Young Seok; Park, Ju Hyuk, Susceptor for semiconductor substrate processing apparatus.
  109. Dunn, Todd; Alokozai, Fred; Winkler, Jerry; Halpin, Michael, Susceptor heater and method of heating a substrate.
  110. Dunn, Todd; White, Carl; Halpin, Michael; Shero, Eric; Winkler, Jerry, Susceptor heater shim.
  111. Tang, Fu; Givens, Michael Eugene; Xie, Qi; Raisanen, Petri, System and method for gas-phase sulfur passivation of a semiconductor surface.
  112. Lawson, Keith R.; Givens, Michael E., Systems and methods for dynamic semiconductor process scheduling.
  113. Sarin, Michael Christopher; Mendez, Rafael; Bartlett, Gregory M.; Hill, Eric; Lawson, Keith R.; Rosser, Andy, Systems and methods for mass flow controller verification.
  114. Yu, Hong Yu; Li, Ming Fu; Kwong, Dim Lee; Bera, Lakshmi Kanta, Thermal robust semiconductor device using HfN as metal gate electrode and the manufacturing process thereof.
  115. Ramaswamy, D. V. Nirmal; Iyer, Ravi, Transistor gate forming methods and integrated circuits.
  116. Ramaswamy, D. V. Nirmal; Iyer, Ravi, Transistor gate forming methods and integrated circuits.
  117. Cartier, Eduard A.; Copel, Matthew W.; Doris, Bruce B.; Jammy, Rajarao; Kim, Young Hee; Linder, Barry P.; Narayanan, Vijay; Paruchuri, Vamsi K.; Wong, Keith Kwong Hon, Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices.
  118. Cartier, Eduard A.; Copel, Matthew W.; Doris, Bruce B.; Jammy, Rajarao; Kim, Young-Hee; Linder, Barry P.; Narayanan, Vijay; Paruchuri, Vamsi K.; Wong, Keith Kwong Hon, Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices.
  119. Coomer, Stephen Dale, Variable adjustment for precise matching of multiple chamber cavity housings.
  120. Shugrue, John Kevin, Variable conductance gas distribution apparatus and method.
  121. Schmotzer, Michael; Whaley, Shawn, Variable gap hard stop design.
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