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A VLIW processor for executing a sequence of very long instruction words having a plurality of operations to be executed in parallel. The VLIW processor has a plurality of functional units for parallel execution of the operations specified by the VLIW, an instruction register for holding the VLIW, a

A VLIW processor for executing a sequence of very long instruction words having a plurality of operations to be executed in parallel. The VLIW processor has a plurality of functional units for parallel execution of the operations specified by the VLIW, an instruction register for holding the VLIW, and a condition flag for indicating the results of a comparison operation. The VLIW includes a conditional head and a plurality of slots, each slot including an operational code and any related operands. The conditional head has a plurality of conditional indicators, each conditional indicator uniquely corresponding to one operation and specifying a condition in which the operation is to be executed if the indicated condition exists. A control circuit is connected to the instruction register and the functional units to deliver the operation from the instruction register to the corresponding functional unit for execution when the condition exists.

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1. A very long instruction word (VLIW) processor for executing a very long instruction word, the VLIW having a conditional execution head (CEX) and a plurality of operations, the VLIW processor comprising:a plurality of functional units for executing operations in parallel; an instruction register h

1. A very long instruction word (VLIW) processor for executing a very long instruction word, the VLIW having a conditional execution head (CEX) and a plurality of operations, the VLIW processor comprising:a plurality of functional units for executing operations in parallel; an instruction register having a plurality of slots for holding the conditional execution head and the operations, the conditional execution head comprising a plurality of conditional indicators each specifying a condition under which a corresponding operation comprised in the VLIW is to be executed; a plurality of switches each connected to a slot and a functional unit for controlling delivery of an operation from the slot to the functional unit for execution; and a control circuit connected to the instruction register and each switch, the control circuit being capable of opening or closing the switch according to the condition specified in the corresponding conditional indicator; wherein functional units which are connected to opened switches will receive operations from slots connected to the switches, functional units which are connected to closed switches will be prohibited from receiving operations, and operations which are received by functional units will be executed in parallel. 2. The VLIW processor of claim 1 wherein each conditional indicator uniquely corresponds to only one operation comprised in the VLIW and each operation uniquely corresponds to only one conditional indicator comprised in the conditional execution head.3. The VLIW processor of claim 1 wherein the operation comprises an operational code specifying the operation to be executed by the functional unit.4. The VLIW processor of claim 1 further comprises a condition flag indicating the results of a comparison operation.5. The VLIW processor of claim 4 wherein the conditional indicator is a single bit.6. The VLIW processor of claim 5 wherein the condition to execute the operation is met when the conditional indicator and the condition flag are set to the same value.7. A very long instruction word (VLIW) processor having a plurality of functional units for executing a very long instruction word, the VLIW comprising a conditional execution head (CEX) and a plurality of operations, the maximum number of operations to be executed being equal to the number of functional units, the VLIW processor comprising:an instruction register having a plurality of slots for holding the conditional execution head and the operations, the conditional execution head comprising a plurality of conditional indicators, the number of conditional indicators being equal to the number of operations comprised in the VLIW and each conditional indicator uniquely corresponding to only one operation, each conditional indicator indicating a condition under which the corresponding operation is to be executed; a plurality of switches for controlling the delivery of the operation from the instruction register to the functional unit, each switch connecting only one slot and only one functional unit in a one-to-one correspondence; and a control circuit connected to the instruction register and the switch, the control circuit capable of opening the switch when the condition indicating the corresponding operation is to be executed is met and for closing the switch when the condition indicating the corresponding operation is to be executed is not met. 8. The VLIW processor of claim 7 wherein the operation comprises an operational code specifying the operation to be executed by the functional unit.9. The VLIW processor of claim 7 further comprises a condition flag indicating the results of a comparison operation.10. The VLIW processor of claim 9 wherein the condition to execute the operation is met when the conditional indicator and the condition flag are set to the same value.11. A method of program execution by a very long instruction word (VLIW) processor, the VLIW comprising a conditional execution head (CEX) and a plurality of operations, the conditional head comprising a plurality of conditional indicators, each conditional indicator corresponding to a predetermined operation and for specifying a condition when the operation is to be executed, the VLIW processor comprising an instruction register having a plurality of slots for holding the conditional execution head and the operations, a plurality of functional units for executing operations in parallel, and a plurality of switches, each switch in a one-to-one correspondence with and connected between only one slot and only one functional unit, the switch for controlling delivery of the operation to the functional unit, the method comprising:opening the switch when the condition specified by the conditional indicator is met and closing the switch when the condition specified by the conditional indicator is not met. 12. The method of claim 11 wherein the VLIW processor further comprises a condition flag indicating the results of a comparison operation.13. The method of claim 12 wherein the condition to execute the operation is met when the conditional indicator and the condition flag are set to the same value.