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An electronic device, and SRAM and a method of forming the electronic device and SRAM. The semiconductor device including: a pass gate transistor having a fin body having opposing sidewalls aligned in a first direction and having a first majority carrier mobility and a gate adjacent to both sidewall

An electronic device, and SRAM and a method of forming the electronic device and SRAM. The semiconductor device including: a pass gate transistor having a fin body having opposing sidewalls aligned in a first direction and having a first majority carrier mobility and a gate adjacent to both sidewalls of the fin body; a pull down latch transistor having a fin body having opposing sidewalls aligned in a second direction and having a second majority carrier mobility and a gate adjacent to both sidewalls of thc fin body; a pull up latch transistor having a fin body having opposing sidewalls aligned in a third direction and having a third majority carrier mobility and a gate adjacent to both sidewalls of the fin body; and CMOS chevron logic circuits, wherein crystal planes of each fin body and of CMOS transistor of the chevron logic are co-aligned.

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1. An electronic device comprising:a semiconductor device comprising: a pass gate transistor including a first fin body and a first gate, said first fin body having opposing sidewalls, each sidewall aligned in a first direction having a first majority carrier mobility, said first gate adjacent to bo

1. An electronic device comprising:a semiconductor device comprising: a pass gate transistor including a first fin body and a first gate, said first fin body having opposing sidewalls, each sidewall aligned in a first direction having a first majority carrier mobility, said first gate adjacent to both sidewalls or said first fin body; a pull down latch transistor including a second fin body and a second gate, said second fin body having opposing sidewalls, each sidewall aligned in a second direction having a second majority carrier mobility, said second gate adjacent to both sidewalls of said second fin body; a pull up latch transistor including a third fin body and a third gate, said third fin body having opposing sidewalls, each sidewall aligned in a third direction having a third majority carrier mobility, said third gate adjacent to both sidewalls of said third fin body; wherein all of said first, second and third directions are not the same direction; and one or more CMOS chevron logic circuits, crystal planes of bodies of transistors of said CMOS chevron logic circuits and crystal planes of said first, second and third fin bodies co-aligned. 2. The semiconductor device of claim 1, wherein said first and second directions are parallel to a {100} crystal plane of said fin bodies and said third direction is aligned between said {100} crystal plane and a {110} crystal plane of said fin bodies.3. The semiconductor device of claim 2, wherein said third direction is halfway between said {100} crystal plane and said {110} crystal plane.4. The semiconductor device of claim 1, wherein said first majority carrier mobility is a high majority carrier mobility, said second majority carrier mobility is a high majority carrier mobility and said third majority carrier mobility is a medium majority carrier mobility.5. The semiconductor device of claim 1, wherein said second direction is parallel to a {100} crystal plane of said fin bodies and said first and third directions and aligned between said {100} crystal plane and a {110} crystal plane of said fin bodies.6. The semiconductor device of claim 5, wherein said first and third directions are in a same direction which bisects an angle between said {100} crystal plane and said {110} crystal plane.7. The semiconductor device of claim 1, wherein said first majority carrier mobility is a high majority carrier mobility, said second majority carrier mobility is a medium majority carrier mobility and said third majority carrier mobility is a medium majority carrier mobility.8. The semiconductor device of claim 1, wherein said first, second and third directions each bisects an angle between said {100} and a {110} crystal planes of said first, second and third fin bodies respectively.9. The semiconductor device of claim 8, wherein said first, second and third direction are equal and halfway between said {100} crystal plane and said {110} crystal plane.10. The semiconductor device of claim 1, wherein said first majority carrier mobility is a medium majority carrier mobility, said second majority carrier mobility is a medium majority carrier mobility and said third majority carrier mobility is a medium majority carrier mobility.11. The semiconductor device of claim 1, wherein said first fin body and said second fin body are contiguous.12. The semiconductor device of claim 1, wherein said second and third gates are contiguous.13. The semiconductor device of claim 1, wherein:said first fin body includes two fin portions, each fin portion having opposing sidewalls, said fin portions separated by a gap; and wherein said first gate is adjacent to both sidewalls of both fin portions. 14. The semiconductor device of claim 1, wherein said pass gate transistor and said pull down transistor latch are NFBTs and said pull-up latch transistor is a PFET.15. A method of fabricating a semiconductor device comprising:forming a first fin body of a pass gate transistor from a crystal layer, said first fin body having opposing sidewalls, each sidewall aligned in a first direction having a first majority carrier mobility; forming a second fin body of a pull down latch transistor from said crystal layer, said second fin body having opposing sidewalls, each sidewall aligned in a second direction having a second majority carrier mobility; forming a third fin body of a pull up latch transistor from said crystal layer said third fin body having opposing sidewalls, each sidewall aligned in a first direction having a third majority carrier mobility; and forming a first gate adjacent to bath sidewalls of said first fin body, a second gate adjacent to both sidewalls of said second fin body and a third gate adjacent to both sidewalls of said third fin body wherein all of said first, second and third directions are not the same direction; and forming bodies of CMOS devices of one or more CMOS chevron logic circuits from said crystal layer. 16. The method of claim 15, wherein said first and second directions are parallel to a {100} crystal plane of said fin bodies and said third direction is aligned between said {100} crystal plane and a {110} crystal plane of said fin bodies.17. The method of claim 16, wherein said third direction is halfway between said {100} crystal plane and said {110} crystal plane.18. The method device of claim 15, wherein said first majority carrier mobility is a high majority carrier mobility, said second majority carrier mobility is a high majority carrier mobility and said third majority carrier mobility is a medium majority carrier mobility.19. The method of claim 15, wherein said second direction is parallel to a {100} crystal plane of said fin bodies and said first and third directions and aligned between said {100} crystal plane and a {110} crystal plane of said fin bodies.20. The method of claim 19, wherein said first and third directions are in a same direction which bisects an angle between said {100} crystal plane and said {110} crystal plane.21. The method of claim 15, wherein said first majority carrier mobility is a high majority carrier mobility, said second majority carrier mobility is a medium majority carrier mobility and said third majority carrier mobility is a medium majority carrier mobility.22. The method of claim 15, wherein said first, second and third directions are aligned between said {100} and a {110} crystal planes of said fin bodies.23. The method of claim 22, wherein said first, second and third directions each bisects an angle between said {100} and a {110} crystal planes of said first, second and third fin bodies respectively.24. The method of claim 15, wherein said first majority carrier mobility is a medium majority carrier mobility, said second majority carrier mobility is a medium majority carrier mobility and said third majority carrier mobility is a medium majority carrier mobility.25. The method of claim 15, wherein said first fin body and said second fin body are contiguous.26. The method of claim 15, wherein said second and third gates are contiguous.27. The method of claim 15, wherein:said first fin body includes two fin portions, each fin portion having opposing sidewalls, said fin portions separated by a gap; and wherein said first gate is adjacent to both sidewalls of both fin portions. 28. The method of claim 15, wherein said pass gate transistor and said pull down latch transistor are NFETs and said pull-up latch transistor is a PFET.29. An electronic device comprising:an SRAM cell comprising: first and second pass gate transistors, each pass gate transistor, including a fin body and a gate, said first fin bodies each having opposing sidewalls and each sidewall aligned in a first direction having a first majority carrier mobility, said gate adjacent to both sidewalls; first and second pull down latch transistors, each pull down transistor including a fin body and a gate, each fin body having opposing sidewalls and each sidewall aligned in a second direction having a second majority carrier mobility, said gate adjacent to both sidewalls; first and second pull down latch transistors, each pull down transistor including a fin body and a gate, each fin body having opposing sidewalls and each sidewall aligned in a third direction having a third majority carrier mobility, said gate adjacent to both sidewalls, said third direction aligned between {100} crystal plane and a {110} crystal plane of said fin bodies of said first and second pull up latch transistors; and wherein all of said first, second and third directions are not the same direction; and one or more CMOS chevron logic circuits, crystal planes of bodies of transistors of said CMOS chevron logic circuits co-aligned with crystal planes of said fin bodies of said pass gate transistors, said pull down latch transistors and said pull up latch transistors. 30. The SRAM cell of claim 29, wherein said first and second directions are aligned with said {100} crystal plane, said first direction is aligned with said {100} crystal plane and said second direction bisects an angle between said {100} and {110} crystal planes, or both said first and second directions each bisect the angle between said {100} and {110} crystal planes.