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Method and system for periodically measuring the junction temperature of a semiconductor device. The junction exited by at least two sequential predetermined currents of different magnitudes the voltage response of the junction to the at least two currents is measured and the temperature of the junc

Method and system for periodically measuring the junction temperature of a semiconductor device. The junction exited by at least two sequential predetermined currents of different magnitudes the voltage response of the junction to the at least two currents is measured and the temperature of the junction is calculated, while substantially canceling ohmic effects, by using the voltage response and a correction factor obtained by periodically. Whenever desired, the junction is exited by a set of at least four sequential different currents having known ratios. The voltage response to the set is measured and the correction factor is calculated by using each voltage response to the set.

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1. A method for periodically measuring the junction temperature of a semiconductor device, comprising:exciting said junction by at least two sequential predetermined currents of different magnitudes; measuring the voltage response of said junction to said at least two currents; and calculating the t

1. A method for periodically measuring the junction temperature of a semiconductor device, comprising:exciting said junction by at least two sequential predetermined currents of different magnitudes; measuring the voltage response of said junction to said at least two currents; and calculating the temperature of said junction, while substantially canceling ohmic effects, by using said voltage response and a correction factor obtained by: exciting said junction by a set of at least four sequential different currents having known ratios; measuring the voltage response to said set; and calculating said correction factor by using each voltage response to said set. 2. A method, comprising:determining a correction factor used to at least partially correct for error in determining a temperature of a semiconductor junction; providing a plurality of currents to the junction; measuring a plurality of voltage responses at the junction; and determining the temperature of the junction using the voltage responses and the correction factor. 3. The method of claim 2, wherein:the plurality of voltage responses include first and second voltage responses; and determining the temperature of the junction comprises determining the temperature of the junction using a formula of T=C*(V2?V1?K), where T represents the temperature of the junction, C represents a constant, V2 represents the second voltage response, V1 represents the first voltage response, and K represents the correction factor. 4. The method of claim 2, wherein determining the correction factor comprises:providing a plurality of additional currents to the junction; measuring a plurality of additional voltage responses at the junction; and determining the correction factor using the additional voltage responses. 5. The method of claim 4, wherein:the plurality of additional currents include first, second, third and fourth additional currents; the plurality of additional voltage responses include first, second, third, and fourth additional voltage responses; and determining the correction factor comprises: determining a first voltage difference between the first and second additional voltage responses; determining a second voltage difference between the third and fourth additional voltage responses; and determining a difference between the first and second voltage differences, the correction factor based on the difference between the first and second voltage differences. 6. The method of claim 5, wherein the correction factor is obtained by multiplying the difference between the first and second voltage differences by a constant, the constant based on a ratio of the first and third additional currents.7. The method of claim 5, wherein a ratio of the first and second additional currents equals a ratio of the third and fourth additional currents.8. The method of claim 4, wherein providing the plurality of additional currents comprises:generating a reference current; generating a plurality of first mirrored reference currents using the reference current, each first mirrored reference current equaling the reference current; generating a plurality of second mirrored reference currents using the first mirrored reference currents, each second mirrored reference current equaling a sum of at least one first mirrored reference current; and providing different combinations of the second mirrored reference currents as the plurality of additional currents. 9. The method of claim 4, wherein determining the correction factor comprises:converting the additional voltage responses into digital bit streams, each digital bit stream associated with one of the additional voltage responses and having a ratio of ones to zeros that is proportional to a ratio of the associated additional voltage response to a reference signal; and determining the correction factor using the digital bit streams. 10. The method of claim 9, wherein:the plurality of additional voltage responses comprise first, second, third, and fourth additional voltage responses; and determining the correction factor using the digital bit streams comprises: initializing a value in a counter; incrementing the value in the counter for each one value in the digital bit stream associated with the fourth additional voltage response; decrementing the value in the counter for each one value in the digital bit stream associated with the third additional voltage response; incrementing the value in the counter for each one value in the digital bit stream associated with the first additional voltage response; and decrementing the value in the counter for each one value in the digital bit stream associated with the second additional voltage response, wherein the correction factor is determined using the value in the counter. 11. The method of claim 10, wherein initializing the value in the counter comprises loading an initial value into the counter.12. The method of claim 10, wherein:the plurality of voltage responses comprise first and second voltage responses; and determining the temperature of the junction comprises: inverting the determined correction factor; loading the inverted correction factor into the counter; incrementing the value in the counter for each one value in a digital bit stream associated with the second voltage response; and decrementing the value in the counter for each one value in a digital bit stream associated with the first voltage response, wherein the temperature is determined using the value in the counter. 13. The method of claim 2, wherein determining the correction factor comprises determining the correction factor in response to at least one of a specified time period elapsing and a number of temperature determinations being performed.14. The method of claim 2, wherein the error comprises error introduced by parasitic Ohmic resistances in the junction.15. The method of claim 2, wherein the junction comprises a transistor.16. A system, comprising:a current generator operable to generate a plurality of currents and to supply the plurality of currents to a semiconductor junction; a voltage monitor operable to measure a plurality of voltage responses at the junction; and a temperature monitor operable to determine a temperature of the junction using the plurality of voltage responses and a correction factor, the correction factor at least partially correcting for error in determining the temperature of the junction. 17. The system of claim 16, wherein:the plurality of currents include first and second currents; the plurality of voltage responses include first and second voltage responses; and the temperature monitor is operable to determine the temperature of the junction using a formula of T=C*(V2?V1?K), where T represents the temperature of the junction, C represents a constant, V2 represents the second voltage response, V1 represents the first voltage response, and K represents the correction factor. 18. The system of claim 16, wherein:the current generator is further operable to provide a plurality of additional currents to the junction; the voltage monitor is further operable to measure a plurality of additional voltage responses at the junction; and the temperature monitor is further operable to determine the correction factor using the additional voltage responses. 19. The system of claim 18, wherein:the plurality of additional voltage responses include first, second, third, and fourth additional voltage responses; and the temperature monitor is operable to determine the correction factor by: determining a first voltage difference between the first and second additional voltage responses; determining a second voltage difference between the third and fourth additional voltage responses; and determining a difference between the first and second voltage differences, the correction factor based on the difference between the first and second voltage differences. 20. The system of claim 18, wherein:the plurality of additional voltage responses include first, second, third, and fourth additional voltage responses; and the temperature monitor comprises: an analog-to-digital converter operable to convert each additional voltage response into digital bit streams, each digital bit stream associated with one of the additional voltage responses and having a ratio of ones to zeros that is proportional to a ratio of the associated additional voltage response to a reference signal; and a counter operable to increment a value in the counter for each one value in the digital bit stream associated with the fourth additional voltage response, decrement the value in the counter for each one value in the digital bit stream associated with the third additional voltage response, increment the value in the counter for each one value in the digital bit stream associated with the first additional voltage response, and decrement the value in the counter for each one value in the digital bit stream associated with the second additional voltage response, wherein the correction factor is determined using the value in the counter. 21. The system of claim 20, wherein:the plurality of voltage responses comprise first and second voltage responses; the temperature monitor further comprises a register operable to store the determined correction factor; and the temperature monitor is operable to determine the temperature of the junction by: inverting the determined correction factor in the register; loading the inverted correction factor into the counter; incrementing the value in the counter for each one value in a digital bit stream associated with the second voltage response; and decrementing the value in the counter for each one value in a digital bit stream associated with the first voltage response, wherein the temperature is determined using the value in the counter. 22. The system of claim 16, wherein the current generator comprises:a current source operable to generate a reference current; a first mirror stage operable to generate a plurality of first mirrored reference currents using the reference current, each first mirrored reference current equaling the reference current; a second mirror stage operable to generate a plurality of second mirrored reference currents using the first mirrored reference currents, each second mirrored reference current equaling a sum of at least one first mirrored reference current, the second mirror stage further operable to provide different combinations of the second mirrored reference currents as the plurality of additional currents. 23. The system of claim 22, wherein:the first mirror stage comprises: a plurality of first transistors coupled in parallel, each first transistor operable to generate one of the first mirrored reference currents; a second transistor coupled in series with the plurality of first transistors and operable to sum at least one of the first mirrored reference currents; and the second mirror stage comprises: a plurality of third transistors coupled in parallel, each third transistor operable to generate one of the second mirrored reference currents; and a plurality of switches, each switch coupled in series with one of the third transistors. 24. A system, comprising:means for providing a plurality of currents to a semiconductor junction; means for measuring a plurality of voltage responses at the junction; and means for determining a temperature of the junction using the plurality of voltage responses and a correction factor, the correction factor at least partially correcting for error in determining the temperature of the junction. 25. A method, comprising:providing a plurality of currents to a semiconductor junction; measuring a plurality of voltage responses at the junction; and determining a correction factor using the voltage responses, the correction factor used to at least partially correct for error in determining a temperature of the junction. 26. The method of claim 25, wherein:the plurality of voltage responses include first, second, third, and fourth voltage responses; and determining the correction factor comprises: determining a first voltage difference between the first and second voltage responses; determining a second voltage difference between the third and fourth voltage responses; and determining a difference between the first and second voltage differences, the correction factor based on the difference between the first and second voltage differences. 27. The method of claim 25, wherein determining the correction factor comprises:converting the voltage responses into digital bit streams, each digital bit stream associated with one of the voltage responses and having a ratio of ones to zeros that is proportional to a ratio of the voltage response to a reference signal; initializing a value in a counter; incrementing the value in the counter for each one value in the digital bit stream associated with the fourth voltage response; decrementing the value in the counter for each one value in the digital bit stream associated with the third voltage response; incrementing the value in the counter for each one value in the digital bit stream associated with the first voltage response; and decrementing the value in the counter for each one value in the digital bit stream associated with the second voltage response, wherein the correction factor is determined using the value in the counter. 28. The method of claim 25, wherein providing the plurality of currents comprises:generating a reference current; generating a plurality of first mirrored reference currents using the reference current, each first mirrored reference current equaling the reference current; generating a plurality of second mirrored reference currents using the first mirrored reference currents, each second mirrored reference current equaling a sum of at least one first mirrored reference current; and providing different combinations of the second mirrored reference currents as the plurality of currents. 29. A system, comprising:a current generator operable to generate a plurality of currents and to supply the plurality of currents to a semiconductor junction; a voltage monitor operable to measure a plurality of voltage responses at the junction; and a correction unit operable to determine a correction factor using the voltage responses, the correction factor used to at least partially correct for error in determining a temperature of the semiconductor junction. 30. The system of claim 29, wherein:the plurality of voltage responses include first, second, third, and fourth voltage responses; and the correction unit is operable to determine the correction factor by: determining a first voltage difference between the first and second voltage responses; determining a second voltage difference between the third and fourth voltage responses; determining a difference between the first and second voltage differences, the correction factor based on the difference between the first and second voltage differences. 31. The system of claim 29, wherein:the plurality of voltage responses include first, second, third, and fourth voltage responses; and the correction unit comprises: an analog-to-digital converter operable to convert each voltage response into digital bit streams, each digital bit stream associated with one of the voltage responses and having a ratio of ones to zeros that is proportional to a ratio of the associated voltage response to a reference signal; and a counter operable to increment a value in the counter for each one value in the digital bit stream associated with the fourth voltage response, decrement the value in the counter for each one value in the digital bit stream associated with the third voltage response, increment the value in the counter for each one value in the digital bit stream associated with the first voltage response, and decrement the value in the counter for each one value in the digital bit stream associated with the second voltage response, wherein the correction factor is determined using the value in the counter. 32. The system of claim 29, wherein the current generator comprises:a current source operable to generate a reference current; a first mirror stage operable to generate a plurality of first mirrored reference currents using the reference current, each first mirrored reference current equaling the reference current; and a second mirror stage operable to generate a plurality of second mirrored reference currents using the first mirrored reference currents, each second mirrored reference current equaling a sum of at least one first mirrored reference current, the second mirror stage further operable to provide different combinations of the second mirrored reference currents as the plurality of currents. 33. The system of claim 32, wherein:the first mirror stage comprises: a plurality of first transistors coupled in parallel, each first transistor operable to generate one of the first mirrored reference currents; a second transistor coupled in series with the plurality of first transistors and operable to sum at least one of the first mirrored reference currents; and the second mirror stage comprises: a plurality of third transistors coupled in parallel, each third transistor operable to generate one of the second mirrored reference currents; and a plurality of switches, each switch coupled in series with one of the third transistors.