IPC분류정보
| 국가/구분 |
United States(US) Patent
등록
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| 국제특허분류(IPC7판) |
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| 출원번호 |
US-0365091
(2003-02-11)
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발명자
/ 주소 |
- Thurgood, Blaine
- Corisis, David
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| 출원인 / 주소 |
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| 대리인 / 주소 |
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| 인용정보 |
피인용 횟수 :
3 인용 특허 :
129 |
초록
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Methods and apparatuses for packaging a microelectronic device. One embodiment can include a packaged microelectronic device comprising a microelectronic die, an interposer substrate, and a casing encapsulating at least a portion of the die. The microelectronic die can have a first side attached to
Methods and apparatuses for packaging a microelectronic device. One embodiment can include a packaged microelectronic device comprising a microelectronic die, an interposer substrate, and a casing encapsulating at least a portion of the die. The microelectronic die can have a first side attached to the substrate, a plurality of contacts on the first side, and an integrated circuit coupled to the contacts. The die can also include a second side with a plurality of first interconnecting elements on the second side of the die, such as first non-planar features. The casing can include an interior surface and a plurality of second interconnecting elements on the interior surface, such as second non-planar features. The first non-planar features on the second side of the die mate with second non-planar features on the interior surface of the casing. Accordingly, delamination along the interface between the microelectronic die and the casing is inhibited.
대표청구항
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1. A packaged microelectronic device, comprising:a redistribution member having an interposer substrate with a plurality of terminals, an array of ball-pads, and traces electrically coupling the terminals to the ball-pads; a microelectronic die including integrated circuitry, an active side adjacent
1. A packaged microelectronic device, comprising:a redistribution member having an interposer substrate with a plurality of terminals, an array of ball-pads, and traces electrically coupling the terminals to the ball-pads; a microelectronic die including integrated circuitry, an active side adjacent to the interposer substrate and having a plurality of bond-pads electrically coupled to the terminals, and a backside, wherein the backside of the die includes a surface and a first non-planar feature relative to the surface; and a casing comprising a mold compound, the casing having an interior surface covering at least a portion of the backside of the die, wherein the interior surface of the casing includes a second non-planar feature engaged with the first non-planar feature of the die, wherein the first and second non-planar features have a height and/or a depth of greater than 25 μm to approximately 200 μm. 2. The microelectronic device of claim 1 wherein:the backside of the die includes a plurality of first non-planar features defined by recesses; and the interior surface of the casing includes a plurality of second non-planar features defined by protrusions that mate with the first non-planar features. 3. The microelectronic device of claim 1 wherein:the backside of the die includes a plurality of first non-planar features defined by recesses; the interior surface of the casing includes a plurality of second non-planar features defined by protrusions that mate with the first non-planar features; and the first and second non-planar features are rectilinear. 4. The microelectronic device of claim 1 wherein:the backside of the die includes a plurality of first non-planar features defined by recesses; the interior surface of the casing includes a plurality of second non-planar features defined by protrusions that mate with the first non-planar features; and the first and second non-planar features are arcuate. 5. The microelectronic device of claim 1 wherein:the backside of the die includes a plurality of first non-planar features defined by recesses; the interior surface of the casing includes a plurality of second non-planar features defined by protrusions that mate with the first non-planar features; and the first and second non-planar features are conical. 6. The microelectronic device of claim 1 wherein:the backside of the die includes a plurality of first non-planar features defined by recesses; the interior surface of the casing includes a plurality of second non-planar features defined by protrusions that mate with the first non-planar features; and the first and second non-planar features are pyramidical. 7. The microelectronic device of claim 1 wherein:the backside of the die includes a plurality of first non-planar features defined by protrusions; and the interior surface of the casing includes a plurality of second non-planar features defined by recesses that mate with the first non-planar features. 8. The microelectronic device of claim 1 wherein:the backside of the die includes a plurality of first non-planar features defined by protrusions; the interior surface of the casing includes a plurality of second non-planar features defined by recesses that mate with the first non-planar features; and the first and second non-planar features are rectilinear. 9. The microelectronic device of claim 1 wherein:the backside of the die includes a plurality of first non-planar features defined by protrusions; the interior surface of the casing includes a plurality of second non-planar features defined by recesses that mate with the first non-planar features; and the first and second non-planar features are arcuate. 10. The microelectronic device of claim 1 wherein:the backside of the die includes a plurality of first non-planar features defined by protrusions; the interior surface of the casing includes a plurality of second non-planar features defined by recesses that mate with the first non-planar features; and the first and second non-planar features are conical. 11. The microelectronic device of claim 1 wherein:the backside of the die includes a plurality of first non-planar features defined by protrusions; the interior surface of the casing includes a plurality of second non-planar features defined by recesses that mate with the first non-planar features; and the first and second non-planar features are pyramidical. 12. The microelectronic device of claim 1 wherein:the backside of the die includes a plurality of first non-planar features defined by ridges; and the interior surface of the casing includes a plurality of second non-planar features defined by trenches that mate with the first non-planar features. 13. The microelectronic device of claim 1 wherein:the backside of the die includes a plurality of first non-planar features defined by parallel ridges; and the interior surface of the casing includes a plurality of second non-planar features defined by trenches that mate with the first non-planar features. 14. The microelectronic device of claim 1 wherein:the backside of the die includes a plurality of first non-planar features defined by ridges; the interior surface of the casing includes a plurality of second non-planar features defined by trenches that mate with the first non-planar features; a first set of first and second non-planar features is a first configuration and a second set of first and second non-planar features is a second configuration; and the first and second configurations are generally similar. 15. The microelectronic device of claim 1 wherein:the backside of the die includes a first non-planar feature defined by a continuous ridge; and the interior surface of the casing includes a second non-planar feature defined by a trench that mates with the first non-planar feature. 16. The microelectronic device of claim 1 wherein:the backside of the die includes a plurality of first non-planar features defined by trenches; and the interior surface of the casing includes a plurality of second non-planar features defined by ridges that mate with the first non-planar features. 17. A packaged microelectronic device, comprising:a redistribution member having an interposer substrate with a plurality of terminals, an array of ball-pads, and traces electrically coupling the terminals to the ball-pads; a microelectronic die including integrated circuitry, an active side adjacent to the interposer substrate and having a plurality of bond-pads electrically coupled to the terminals, and a backside, wherein the backside of the die includes a first interconnecting element; and a casing comprising a mold compound, the casing having an interior surface facing the backside of the die and including a second interconnecting element engaged with the first interconnecting element of the die to restrict relative movement between the backside of the die and the interior surface of the casing, wherein the first and second interconnecting elements have a height and/or a depth of greater than 25 μm to approximately 200 μm. 18. The microelectronic device of claim 17 wherein:the backside of the die includes a plurality of first interconnecting elements defined by recesses; and the interior surface of the casing includes a plurality of second interconnecting elements defined by protrusions that mate with the first interconnecting elements. 19. The microelectronic device of claim 17 wherein:the backside of the die includes a plurality of first interconnecting elements defined by recesses; the interior surface of the casing includes a plurality of second interconnecting elements defined by protrusions that mate with the first interconnecting elements; and the first and second interconnecting elements are rectilinear. 20. The microelectronic device of claim 17 wherein:the backside of the die includes a plurality of first interconnecting elements defined by recesses; the interior surface of the casing includes a plurality of second interconnecting elements defined by protrusions that mate with the first interconnecting elements; and the first and second interconnecting elements are arcuate. 21. The microelectronic device of claim 17 wherein:the backside of the die includes a plurality of first interconnecting elements defined by recesses; the interior surface of the casing includes a plurality of second interconnecting elements defined by protrusions that mate with the first interconnecting elements; and the first and second interconnecting elements are conical. 22. The microelectronic device of claim 17 wherein:the backside of the die includes a plurality of first interconnecting elements defined by recesses; the interior surface of the casing includes a plurality of second interconnecting elements defined by protrusions that mate with the first interconnecting elements; and the first and second interconnecting elements are pyramidical. 23. The microelectronic device of claim 17 wherein:the backside of the die includes a plurality of first interconnecting elements defined by protrusions; and the interior surface of the casing includes a plurality of second interconnecting elements defined by recesses that mate with the first interconnecting elements. 24. The microelectronic device of claim 17 wherein:the backside of the die includes a plurality of first interconnecting elements defined by protrusions; the interior surface of the casing includes a plurality of second interconnecting elements defined by recesses that mate with the first interconnecting elements; and the first and second interconnecting elements are rectilinear. 25. The microelectronic device of claim 17 wherein:the backside of the die includes a plurality of first interconnecting elements defined by protrusions; the interior surface of the casing includes a plurality of second interconnecting elements defined by recesses that mate with the first interconnecting elements; and the first and second interconnecting elements are arcuate. 26. The microelectronic device of claim 17 wherein:the backside of the die includes a plurality of first interconnecting elements defined by protrusions; the interior surface of the casing includes a plurality of second interconnecting elements defined by recesses that mate with the first interconnecting elements; and the first and second interconnecting elements are conical. 27. The microelectronic device of claim 17 wherein:the backside of the die includes a plurality of first interconnecting elements defined by protrusions; the interior surface of the casing includes a plurality of second interconnecting elements defined by recesses that mate with the first interconnecting elements; and the first and second interconnecting elements are pyramidical. 28. A packaged microelectronic device, comprising:a die having integrated circuitry, an active side having a plurality of bond-pads, and a backside having a plurality of first interface elements; a redistribution member coupled to the die, the redistribution member having an array of ball-pads electrically coupled to corresponding bond-pads of the die; and a casing comprising a mold compound enclosing at least a portion of the die and at least a portion of the redistribution member, the casing having an interior surface facing the backside of the die, and the interior surface of the casing including a plurality of second interface elements engaged with corresponding first interface elements to inhibit delamination between the die and the casing along the backside of the die, wherein the first and second interface elements have a height and/or a depth of greater than 25 μm to approximately 200 μm. 29. The microelectronic device of claim 28 wherein:the first interface elements are recesses; and the second interface elements are protrusions that mate with the first interface elements. 30. The microelectronic device of claim 28 wherein:the first interface elements are recesses; the second interface elements are protrusions that mate with the first interface elements; and the first and second interface elements are rectilinear. 31. The microelectronic device of claim 28 wherein:the first interface elements are recesses; the second interface elements are protrusions that mate with the first interface elements; and the first and second interface elements are arcuate. 32. The microelectronic device of claim 28 wherein:the first interface elements are recesses; the second interface elements are protrusions that mate with the first interface elements; and the first and second interface elements are conical. 33. The microelectronic device of claim 28 wherein:the first interface elements defined by recesses; the second interface elements are protrusions that mate with the first interface elements; and the first and second interface elements are pyramidical. 34. The microelectronic device of claim 28 wherein:the first interface elements are protrusions; and the second interface elements are recesses that mate with the first interface elements. 35. The microelectronic device of claim 28 wherein:the first interface elements are protrusions; the second interface elements are recesses that mate with the first interface elements; and the first and second interface elements are rectilinear. 36. The microelectronic device of claim 28 wherein:the first interface elements are protrusions; the second interface elements are recesses that mate with the first interface elements; and the first and second interface elements are arcuate. 37. The microelectronic device of claim 28 wherein:the first interface elements are protrusions; the second interface elements are recesses that mate with the first interface elements; and the first and second interface elements are conical. 38. The microelectronic device of claim 28 wherein:the first interface elements are protrusions; the second interface elements are recesses that mate with the first interface elements; and the first and second interface elements are pyramidical. 39. The microelectronic device of claim 28 wherein:the first interface elements are ridges; and the second interface elements are trenches that mate with the first interface elements. 40. The microelectronic device of claim 28 wherein:the first interface elements are trenches; and the second interface elements are ridges that mate with the first interface elements. 41. A packaged microelectronic device, comprising:a die having integrated circuitry, an active side including a plurality of bond-pads, and a backside having a recess extending into the die; a redistribution member coupled to the die, the redistribution member having an array of ball-pads electrically coupled to the bond-pads; and a casing comprising a mold compound covering at least a portion of the die and at least a portion of the redistribution member, the casing having an interior surface facing the backside of the die, and the interior surface of the casing conforming to the recess on the backside of the die, wherein the recess has a depth of greater than 25 μm to approximately 200 μm. 42. The microelectronic device of claim 41 wherein the recess extending into the die is rectilinear.43. The microelectronic device of claim 41 wherein the recess extending into the die is arcuate.44. The microelectronic device of claim 41 wherein the recess extending into the die is conical.45. The microelectronic device of claim 41 wherein the recess extending into the die is pyramidical.46. A packaged microelectronic device, comprising:a die having integrated circuitry, an active side including a plurality of bond-pads, and a backside having a protrusion projecting away from the die; a redistribution member coupled to the die, the redistribution member having an array of ball-pads electrically coupled to the bond-pads; and a casing comprising a mold compound covering at least a portion of the die and at least a portion of the redistribution member, the casing having an interior surface facing the backside of the die, and the interior surface of the casing conforming to the protrusion on the backside of the die, wherein the protrusion has a height of greater than 25 μm to approximately 200 μm. 47. The microelectronic device of claim 46 wherein the recess extending into the die is rectilinear.48. The microelectronic device of claim 46 wherein the recess extending into the die is arcuate.49. The microelectronic device of claim 46 wherein the recess extending into the die is conical.50. The microelectronic device of claim 46 wherein the recess extending into the die is pyramidical.51. A method of forming a packaged microelectronic device, comprising:forming an interface element having a height and/or a depth of greater than 25 μm to approximately 200 μm on a backside of a die, the die having an integrated circuit and an active side with bond pads; attaching the die to a redistribution member having an array of ball-pads and electrically coupling the bond-pads to the ball-pads; and molding a die compound to (a) cover at least a portion of the backside of the die and (b) conform to the interface element. 52. The method of claim 51 wherein forming an interface element on the backside of the die comprises depositing material on the backside of the die.53. The method of claim 51 wherein forming an interface element on the backside of the die comprises removing material from the backside of the die.54. The method of claim 51 wherein forming an interface element on the backside of the die comprises forming a plurality of recesses on the backside of the die.55. The method of claim 51 wherein forming an interface element on the backside of the die comprises forming a plurality of protrusions on the backside of the die.56. The method of claim 51 wherein forming an interface element on the backside of the die comprises forming a plurality of ridges on the backside of the die.57. The method of claim 51 wherein forming an interface element on the backside of the die comprises forming a plurality of trenches on the backside of the die.58. The method of claim 51 wherein forming an interface element on the backside of the die comprises etching a recess in the backside of the die.59. The method of claim 51 wherein forming an interface element on the backside of the die comprises laser drilling a recess in the backside of the die.60. A method of forming a packaged microelectronic device having a die including an active side and a backside, wherein the backside includes a planar surface, the method comprising:forming an interface element having a height and/or a depth of greater than 25 μm to approximately 200 μm on the backside of the die, the interface element being non-planar relative to the surface on the backside of the die, and the die having bond-pads on the active side; attaching the die to a redistribution member having an array of ball-pads and electrically coupling the bond-pads to the ball-pads; and molding a die compound to (a) cover at least a portion of the backside of the die and (b) conform to the interface element. 61. The method of claim 60 wherein forming a non-planar interface element on the backside of the die comprises depositing material on the backside of the die.62. The method of claim 60 wherein forming a non-planar interface element on the backside of the die comprises removing material from the backside of the die.63. The method of claim 60 wherein forming a non-planar interface element on the backside of the die comprises forming a plurality of recesses on the backside of the die.64. The method of claim 60 wherein forming a non-planar interface element on the backside of the die comprises forming a plurality of protrusions on the backside of the die.65. The method of claim 60 wherein forming a non-planar interface element on the backside of the die comprises forming a plurality of ridges on the backside of the die.66. The method of claim 60 wherein forming a non-planar interface element on the backside of the die comprises forming a plurality of trenches on the backside of the die.67. A method of forming a packaged microelectronic device having a die including an active side and a backside, wherein the backside includes a planar surface, the method comprising:forming an interconnecting element having a height and/or a depth of greater than 25 μm to approximately 200 μm on the backside of the die, the interconnecting element being non-planar relative to the surface on the backside of the die, and the die having bond-pads on the active side; attaching the die to a redistribution member having an array of ball-pads and electrically coupling the bond-pads to the ball-pads; and molding a die compound to (a) cover at least a portion of the backside of the die and (b) conform to the interconnecting element. 68. A method of forming a packaged microelectronic device having a die including an active side having bond-pads and a backside, wherein the backside includes a planar surface, the method comprising:forming a recess having a depth of greater than 25 μm to approximately 200 μm on the backside of a die; attaching the die to a redistribution member having an array of ball-pads and electrically coupling the bond-pads to the ball-pads; and molding a die compound to (a) cover at least a portion of the backside of the die and (b) conform to the recess on the backside of the die. 69. A method of forming a packaged microelectronic device having a die including an active side having bond-pads and a backside, wherein the backside includes a planar surface, the method comprising:forming a protrusion having a height of greater than 25 μm to approximately 200 μm projecting away from the backside of a die; attaching the die to a redistribution member having an array of ball-pads and electrically coupling the bond-pads to the ball-pads; and molding a die compound to (a) cover at least a portion of the backside of the die and (b) conform to the protrusion on the backside of the die.
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