[특허]Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS

Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/336
출원번호	US-0611739 (2003-07-01)
발명자 / 주소	Fitzgerald, Eugene A. Gerrish, Nicole
출원인 / 주소	AmberWave Systems Corporation
대리인 / 주소	Testa, Hurwitz &
인용정보	피인용 횟수 : 65 인용 특허 : 151

초록 ▼

A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides a method of fabricating an integrated circuit including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.

대표청구항 ▼

1. A method of fabricating a CMOS inverter, the method comprising the steps of:providing a heterostructure including a Si substrate, a Si1-xGex layer on the Si substrate, and a strained layer on the Si1-xGex layer, the heterostructure comprising an interface, located between the strained layer and the Si substrate, that exhibits a roughness less than 1 nm, whereby the strained layer exhibits a surface roughness less than 1 nm; and integrating a pMOSFET and an nMOSFET in the heterostructure, wherein a channel of the pMOSFET and a channel of the nMOSFET are formed in the strained surface layer. 2. The method of claim 1 wherein the Si1-xGex layer is relaxed.3. The method of claim 1 wherein the heterostructure further comprises an underlying insulator layer.4. The method of claim 1 wherein 0.1<x<0.5.5. A method of fabricating an integrated circuit comprising:providing a heterostructure having a Si substrate and a strained layer thereover, the strained layer exhibiting a surface roughness less than 1 nm; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises a channel of at least one of the transistors, the transistors being interconnected in a CMOS circuit. 6. The method of claim 5 wherein the heterostructure further comprises an insulating layer below the strained layer.7. The method of claim 5 wherein the heterostructure further comprises a SiGe graded buffer layer positioned between the relaxed Si1-xGex layer and the Si substrate.8. The method of claim 5 wherein the strained layer comprises Si.9. The method of claim 5 wherein 0.1<x<0.5.10. The method of claim 5 wherein the CMOS circuit comprises a logic gate.11. The method of claim 10 wherein the logic gate is a NOR gate.12. The method of claim 10 wherein the logic gate is an XOR gate.13. The method of claim 10 wherein the logic gate is a NAND gate.14. The method of claim 5 wherein the p-channel transistor serves as a pull-up transistor in the CMOS circuit and the n-channel transistor serves as a pull-down transistor in the CMOS circuit.15. The method of claim 5 wherein the heterostructure further comprises a Si1-xGex layer below the strained layer.16. The method of claim 5 wherein an interface including an unexposed face of the strained layer exhibits a roughness less than 1 nm.

이 특허에 인용된 특허 (151)

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Favors ; Jr. Wesley ; MacDonald Eric William ; Mukherjee Subir ; Warriner Lynn Albert, Voltage controlled oscillator utilizing threshold voltage control of silicon on insulator MOSFETS.
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Terumoto Akatsuka JP; Keisuke Utsunomiya JP, Voltage controlled oscillator with power amplifier.
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Fransis Bert L. ; O'Connor John Francis, Wideband, variable gain amplifier.
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Moroz, Victor; Pramanik, Dipankar, Analysis of stress impact on transistor performance.
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Moroz, Victor; Pramanik, Dipankar, Analysis of stress impact on transistor performance.
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Moroz, Victor; Pramanik, Dipankar, Analysis of stress impact on transistor performance.
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Moroz, Victor; Pramanik, Dipankar, Analysis of stress impact on transistor performance.
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Moroz, Victor; Pramanik, Dipankar, Analysis of stress impact on transistor performance.
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Moroz, Victor; Pramanik, Dipankar, Analysis of stress impact on transistor performance.
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Moroz, Victor; Pramanik, Dipankar, Analysis of stress impact on transistor performance.
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Moroz, Victor; Pramanik, Dipankar, Analysis of stress impact on transistor performance.
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Moroz, Victor; Pramanik, Dipankar, Analysis of stress impact on transistor performance.
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Moroz, Victor; Pramanik, Dipankar, Analysis of stress impact on transistor performance.
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Moroz, Victor; Pramanik, Dipankar, Analysis of stress impact on transistor performance.
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Silverbrook, Kia, Compact nozzle assembly of an inkjet printhead.
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Silverbrook, Kia, Control of a nozzle of an inkjet printhead.
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Fitzgerald,Eugene A., Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization.
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Moroz, Victor; Pramanik, Dipankar; Lin, Xi Wei, Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance.
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Moroz, Victor; Pramanik, Dipankar; Lin, Xi-Wei, Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance.
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Moroz, Victor; Pramanik, Dipankar; Lin, Xi-Wei, Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance.
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Silverbrook, Kia, Energy control of a nozzle of an inkjet printhead.
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Thean,Voon Yew; Vartanian,Victor H.; Winstead,Brian A., Engineering strain in thick strained-SOI substrates.
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Sadaka,Mariam G.; Thomas,Shawn G.; White,Ted R.; Liu,Chun Li; Barr,Alexander L.; Nguyen,Bich Yen; Thean,Voon Yew, Graded semiconductor layer.
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Currie, Matthew T., Hybrid fin field-effect transistor structures and related methods.
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Choi, Munkang; Moroz, Victor; Lin, Xi-Wei, Increasing ION /IOFF ratio in FinFETs and nano-wires.
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Choi, Munkang; Moroz, Victor; Lin, Xi-Wei, Increasing Ion/Ioff ratio in FinFETs and nano-wires.
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Fiorenza, James; Carroll, Mark; Lochtefeld, Anthony J., Inducement of strain in a semiconductor layer.
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Ma,Qing; Lee,Jin; Fujimoto,Harry; Dai,Changhong; Lee,Shiuh Wuu; Eiles,Travis; Seshan,Krishna, Isolation structure configurations for modifying stresses in semiconductor devices.
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Ma,Qing; Lee,Jin; Fujimoto,Harry; Dai,Changhong; Lee,Shiuh Wuu; Eiles,Travis; Seshan,Krishna, Isolation structure configurations for modifying stresses in semiconductor devices.
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Kawa, Jamil; Moroz, Victor, Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits.
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Kawa, Jamil; Moroz, Victor, Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits.
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Kawa, Jamil; Moroz, Victor, Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits.
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Moroz, Victor; Kawa, Jamil, Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits.
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Sharma, Puneet, Layout technique for stress management cells.
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Lin,Xi Wei; Pramanik,Dipankar; Moroz,Victor, Managing integrated circuit stress using dummy diffusion regions.
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Moroz, Victor; Pramanik, Dipankar; Lin, Xi-Wei, Managing integrated circuit stress using stress adjustment trenches.
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Henley,Francois J.; Ong,Philip James; Malik,Igor J., Method and system for lattice space engineering.
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Sadaka, Mariam G.; Barr, Alexander L.; Nguyen, Bich-Yen; Thean, Voon-Yew; White, Ted R., Method for forming a semiconductor structure having a strained silicon layer.
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Lin, Xi Wei; Moroz, Victor; Pramanik, Dipankar, Method of correlating silicon stress to device instance parameters for circuit simulation.
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Silverbrook,Kia, Method of fabricating a micro-electromechanical actuating mechanism.
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Liu,Chun Li; Orlowski,Marius K.; Stoker,Matthew W.; Tobin,Philip J.; Sadaka,Mariam G.; Barr,Alexander L.; Nguyen,Bich Yen; Thean,Voon Yew; Thomas,Shawn G.; White,Ted R., Method of manufacturing SOI template layer.
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Nakamura, Hiroki; Ichikawa, Hiroyuki; Okuno, Eiichi, Method of manufacturing silicon carbide semiconductor device.
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Nakamura, Hiroki; Ichikawa, Hiroyuki; Okuno, Eiichi, Method of manufacturing silicon carbide semiconductor device.
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Fitzgerald,Eugene; Currie,Matthew, Methods for fabricating strained layers on semiconductor substrates.
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Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods for forming III-V semiconductor device structures.
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Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain.
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Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Methods for forming strained-semiconductor-on-insulator device structures by use of cleave planes.
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Fitzgerald, Eugene A., Methods of fabricating contact regions for FET incorporating SiGe.
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Currie,Matthew T., Methods of forming hybrid fin field-effect transistor structures.
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Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods of forming strained-semiconductor-on-insulator device structures.
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Silverbrook, Kia, Nozzle assembly for an inkjet printhead.
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Silverbrook, Kia, Nozzle assembly of an inkjet printhead.
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Falster, Robert J.; Voronkov, Vladimir V.; Pitney, John A.; Albrecht, Peter D., Processes and apparatus for preparing heterostructures with reduced strain by radial compression.
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Falster, Robert J.; Voronkov, Vladimir V.; Pitney, John A.; Albrecht, Peter D., Processes and apparatus for preparing heterostructures with reduced strain by radial distension.
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Fitzgerald,Eugene A., Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits.
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Nguyen, Bich-Yen; Thean, Voon-Yew, Selective uniaxial stress relaxation by layout optimization in strained silicon on insulator integrated circuit.
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Zhang,Da; White,Ted R.; Nguyen,Bich Yen, Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor.
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Liu,Chun Li; Sadaka,Mariam G.; Barr,Alexander L.; Nguyen,Bich Yen; Thean,Voon Yew; Thomas,Shawn G.; White,Ted R.; Xie,Qianghua, Semiconductor layer formation.
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Zhang, Da; Adams, Vance H.; Nguyen, Bich Yen; Grudowski, Paul A., Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors.
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Maa,Jer Shen; Tang,Jinke; Lee,Jong Jan; Tweet,Douglas J.; Hsu,Sheng Teng, Silicon/germanium superlattice thermal sensor.
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Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained germanium-on-insulator device structures.
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Xiang,Qi; Goo,Jung Suk; Wang,Haihong, Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication.
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Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures.
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Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures with elevated source/drain regions.
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Langdo,Thomas A.; Currie,Matthew T.; Braithwaite,Glyn; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator finFET device structures.
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Moroz, Victor; Lin, Xi-Wei; Pramanik, Dipankar, Stress-managed revision of integrated circuit layouts.
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Moroz, Victor; Pramanik, Dipankar; Lin, Xi Wei, Stress-managed revision of integrated circuit layouts.
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Sadaka,Mariam G.; Barr,Alexander L.; Nguyen,Bich Yen; Thean,Voon Yew; White,Ted R., Template layer formation.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

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Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS 원문보기

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연합인증

Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

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이 특허를 인용한 특허 (65)

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