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A tile used to hold one or more probes for testing a semiconductor wafer. The tile has one or more sites for inserting one or more probes to test the semiconductor wafer. Each site has one or more holes. Each hole is coupled with a slot forming an angle. A probe is inserted into the tile from a top

A tile used to hold one or more probes for testing a semiconductor wafer. The tile has one or more sites for inserting one or more probes to test the semiconductor wafer. Each site has one or more holes. Each hole is coupled with a slot forming an angle. A probe is inserted into the tile from a top of the tile through the hole and seated on the slot. The probe has a probe tip. The probe tip is in contact with the semiconductor wafer at one end of the slot at a bottom of the tile. The probe tip is aligned with an X and Y coordinates of a bond pad on the semiconductor wafer.

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1. In a semiconductor wafer testing system where one or more probes are used to test a semiconductor wafer, a tile is used to hold the at least one or more probes for making contacts with the semiconductor wafer, the tile comprising:one or more sites for inserting one or more probes to test the semi

1. In a semiconductor wafer testing system where one or more probes are used to test a semiconductor wafer, a tile is used to hold the at least one or more probes for making contacts with the semiconductor wafer, the tile comprising:one or more sites for inserting one or more probes to test the semiconductor wafer, each site having one or more holes, each hole coupled with a slot forming an angle, wherein a probe is inserted into the tile from a top of the tile through the hole and seated on the slot, the probe having a probe tip in contact with the semiconductor wafer at one end of the slot at a bottom of the tile, wherein the probe tip is aligned with an X and Y coordinates of a bond pad on the semiconductor wafer. 2. The tile of claim 1, wherein the angle formed by the hole and the slot is 90 degrees.3. The tile of claim 1 further comprising a view hole at each site to view the probe tip.4. The tile of claim 1, wherein each of the probes is removable from the tile without affecting remaining probes.5. The tile of claim 4, wherein each of the probes is attached to the tile with epoxy.6. The tile of claim 1, wherein each of the probes has a kink to spring the probe against a wall of the hole in the tile to hold the probe in place.7. The tile of claim 1, wherein each of the probes is attached to an insulated wire.8. In a semiconductor wafer testing system where one or more probes are used to test a semiconductor wafer and where a tile is used to hold the one or more probes for making contacts with the semiconductor wafer, the probe comprising:a probe tip; a cantilever coupled with the probe tip; and a vertical shank coupled with the cantilever and the probe tip, the vertical shank forming an angle with the cantilever to align the probe tip with an X and Y coordinates of a bond pad on the semiconductor wafer, wherein the probe is inserted into the tile through a hole drilled in the tile, and wherein the vertical shank has a kink to retain the probe in the tile. 9. The probe of claim 8, wherein the angle formed by the vertical shank and the cantilever is 90 degrees.10. The probe of claim 8, wherein the kink in the vertical shank springs against a wall of the hole in the tile to hold the probe in place.11. In a test system where one or more probes used to test a substrate, a method, comprising:mounting a tile on a printed circuit board (PCB), wherein: the tile comprises one ore more sites for inserting one or more probes to test the semiconductor wafer, each site having one or more holes, each hole coupled with a slot forming an angle, and the probe comprises a probe tip, a cantilever coupled with the probe tip, and a vertical shank coupled with the cantilever and the probe tip, wherein the probe is inserted into the tile from a top of the tile through the hole and seated on the slot, the vertical shank forming the angle with the cantilever, the angle aligning the probe tip with an X and Y coordinates of a bond pad on the semiconductor wafer; and attaching the probe to the PCB using a spring contact, wherein the probe is removed from the tile by releasing the spring contact. 12. The method of claim 11, wherein the tile and the PCB are separated by a thermal insulating layer when the semiconductor wafer is tested in a high temperature.13. The method of claim 11, wherein a damaged probe is removed from the tile without affecting non-damaged probes inserted in the tile.14. The method of claim 11, wherein the tile further comprises a view hole to view the prove tip.15. The method of claim 11, wherein the angle formed by the vertical shank and the cantilever is 90 degrees.16. The method of claim 11, wherein the vertical shank has a kink to spring against a wall of the hole in the tile to hold the probe in place.