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Early race conditions caused by multiple computer system entities issuing memory reference operations for a given memory block are resolved by creating linked lists identifying the entities. The lists are preferably formed by storing information and state in miss address file (MAF) entries maintaine

Early race conditions caused by multiple computer system entities issuing memory reference operations for a given memory block are resolved by creating linked lists identifying the entities. The lists are preferably formed by storing information and state in miss address file (MAF) entries maintained by the entities. The MAF entries cooperate to form one or more read chains each of which links the entities requesting read access to a particular version of the given memory block. The MAF entries also cooperate to form a single write chain that links the entities requesting write access to the given memory block. When the desired memory block becomes available, the information and state stored at the MAF entries is then utilized by each entity in satisfying its obligations as part of the read and write chains, thereby ensuring that each entity receives the version of the given memory block that it desires.

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1. A method for resolving early races in a computer system having one or more data processing entities and a shared memory organized into a plurality of memory blocks, at least some of the data processing entities configured to issue requests for selected memory blocks, the method comprising the ste

1. A method for resolving early races in a computer system having one or more data processing entities and a shared memory organized into a plurality of memory blocks, at least some of the data processing entities configured to issue requests for selected memory blocks, the method comprising the steps of:providing one or more directories for maintaining status information over the memory blocks; concurrently receiving, at the one or more directories, a plurality of requests from two or more data processing entities for the same memory block; linking the requests received from the set of data processing entities into one or more chains; and storing information representing the one or more chains at the two or more data processing entities. 2. The method of claim 1 wherein the one or more chains include one or more read chains, each read chain linking the data processing entities whose requests for read access are for the same version of a given memory block, and one write chain linking all of the data processing entities that requested write access to the given memory block.3. The method of claim 2 further comprising the steps of:serially processing each request at the one or more directories; updating the status information at the one or more directories in response to the processing of each request; and organizing the one or more chains such that the last data processing entity in the write chain matches the status information at the one or more directories. 4. The method of claim 2 wherein the step of storing information comprises the steps of:providing a data structure at each data processing entity; and configuring the data structure at each data processing entity of a read chain, other than the last entity of the read chain, to store a pointer to a next data processing entity in the read chain. 5. The method of claim 4 further wherein each data structure is further configured for transition among a plurality of read chain states, each read chain state associated with an action specifying the manner by which the desired version of the given memory block is to be supplied to the next data processing entity in the read chain.6. The method of claim 5 wherein the action associated with a first read chain state is to supply the desired version of the given memory block as part of a regular data passing message.7. The method of claim 6 wherein the action associated with a second read chain state is to supply the desired version of the given memory block as part of a chain data passing message.8. The method of claim 7 whereinthe regular data passing message is a Fill command, the chain data passing message is a Chain_Fill command, the Chain_Fill command is utilized to supply the appropriate version of the given memory block to each data processing entity of the read chain, except for the entity that was the first to have requested read access to the given memory block, and the Fill command is utilized to supply the appropriate version of the given memory block to the entity that was the first to have requested read access to the given memory block. 9. The method of claim 7 whereinthe data structure is a miss address file (MAF) configured to track outstanding requests for memory blocks issued to the shared memory, and each MAF entry has a read pointer field for storing an identifier (ID) assigned to the selected entity in the read chain, and a read chain state field for storing the read chain state of the respective MAF entry. 10. The method of claim 1 wherein the data processing entities include one of processors and input/output (I/O) subsystems.11. The method of claim 2 whereinthe one write chain starts at the entity that was the first to have requested write access to the given memory block and ends at the last entity to have requested write access to the given memory block, and the step of storing information comprises the steps of: providing a data structure at each data processing entity; and configuring the data structure at each data processing entity, other than the last entity of the one write chain, to store a pointer to a next entity in the one write chain. 12. The method of claim 11 wherein each data structure is further configured for transition among a plurality of write chain states, each write chain state associated with an action to be taken by the respective data processing entity upon receipt of the given memory block.13. The method of claim 12 whereinthe action associated with a first write chain state is to supply the desired version of the given memory block to the next data processing entity in the one write chain as part of a regular data passing message; and the action associated with a second write chain state is to issue an acknowledgement to a designated entity that the given memory block has been invalidated at the respective data processing entity. 14. The method of claim 13 wherein the designated entity to which the acknowledgement is issued is part of the one write chain.15. The method of claim 11 wherein the data structure is a miss address file (MAF) configured to track outstanding requests for memory blocks issued to the shared memory.16. A data structure configured at a memory device associated with a first data processing entity of a computer system having a plurality of data processing entities and a shared memory organized into a plurality of memory blocks, the data structure for cooperating in the resolution of early races for the memory blocks, the data structure comprising:a read pointer field for storing an identifier (ID) assigned to a data processing entity that has issued a concurrent request for read access to the same memory block as the first data processing entity; a read chain state field for storing a read chain state associated with the data structure that specifies the manner by which the memory block is to be supplied to the data processing entity indicated by the read pointer field; a write pointer field for storing the ID assigned to a data processing entity that has issued a concurrent request for write access to the memory block; and a write chain state field for storing a write chain state associated with the data structure that specifies an action to be taken by the first data processing entity upon receipt of the given memory block. 17. The data structure of claim 16 whereinthe read chain state field transitions the data structure among an Idle state, a One_Forwarded_Read_Pending state and a Multiple_Forwarded_Read_Pending state; and the write chain state field transition the data structure among an Idle state, an Invalidate_Pending state and a Forwarded_Read_Modify_Pending state. 18. The data structure of claim 17 wherein the data processing entity is one of a processor and an input/output (I/O) subsystem of the computer system.19. The data structure of claim 18 wherein the data structure is part of a miss address file (MAF).