[특허]Method and system for distributed testing of electronic devices

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-011/00
출원번호	US-0966541 (2001-09-27)
발명자 / 주소	Klein, Joseph C. Little, Jack C. Hunter, Paul R. Lawrence, Archer R.
출원인 / 주소	Tanisys Technology, Inc.
대리인 / 주소	Baker Botts L.L.P.
인용정보	피인용 횟수 : 47 인용 특허 : 6

초록 ▼

A distributed tester method and system communicates test recipes for testing electronic devices from a host computer over a network to a test site. The test site translates test recipes into test instructions for execution by a test engine that determines the status of the electronic device. For ins

A distributed tester method and system communicates test recipes for testing electronic devices from a host computer over a network to a test site. The test site translates test recipes into test instructions for execution by a test engine that determines the status of the electronic device. For instance, in a tester for testing memory, a test recipe is defined and stored with a host computer to determine test data for storage on the memory device under test at the test site. The host computer controls execution of the test recipe over the network. The test recipe is defined and stored in an XML formatted data file transmitted over the network to a processor at the test site. The test site processor translates the XML formatted data into test instructions for execution by a test engine. The test engine determines whether the memory device under test accurately stores data and provides the results, such as erroneously stored data, to the host computer through the network. A test design host and a global data master also interface with the network to aid the design and storage of test recipes. The distributed test method and system advantageously improves flexibility of testing over a geographically disbursed area and with divergent test recipes and devices under test.

대표청구항 ▼

1. A distributed memory test system comprising:a host computer storing a plurality of different test recipes; plural test sites distributed distal from the host computer, each test site adapted to interface with a memory device under test, each test site having an embedded processor; and a network i

1. A distributed memory test system comprising:a host computer storing a plurality of different test recipes; plural test sites distributed distal from the host computer, each test site adapted to interface with a memory device under test, each test site having an embedded processor; and a network interfaced with the host computer and the plural test sites, the network communicating respective test recipes from the host computer to respective embedded processors for execution by respective test sites, wherein the host computer provides at least one of the test sites with a test recipe different from a recipe provided to another test site. 2. The system of claim 1 wherein the memory device under test comprises a flash memory device.3. The system of claim 1 wherein the memory device under test comprises a fast page DRAM.4. The system of claim 1 wherein the memory device under test comprises an EDO DRAM.5. The system of claim 1 wherein the memory device under test comprises a SDRAM.6. The system of claim 1 wherein the memory device under test comprises a DDR.7. The system of claim 1 wherein the memory device under test comprises a SRAM.8. The system of claim 1 wherein the memory device under test comprises a EEPROM.9. The system of claim 1 wherein the network comprises Ethernet.10. The system of claim 9 wherein the test recipe comprises XML formatted data.11. The system of claim 10 wherein each embedded processor accepts the XML formatted recipe data to generate instructions for testing the memory device under test.12. The system of claim 1 wherein the network comprises a local area network.13. The system of claim 1 wherein the network comprises the internet.14. The system of claim 13 wherein the test recipe comprises XML formatted data communicated from the host computer to a test site using TCP/IP.15. The system of claim 13 wherein the test recipe comprises XML formatted data communicated from the host computer to a test site using NFS.16. The system of claim 1 wherein the test recipe comprises instructions for performing algorithmic testing at the test site.17. The system of claim 1 wherein the test recipe comprises instructions for performing vector testing at the test site.18. The system of claim 1 further comprising:plural host computers interfaced with the network, each host computer having one or more test recipes; wherein each host computer controls tests performed by at least one test site. 19. The system of claim 18 further comprising a test designer interfaced with the network, the test designer operational to create the test recipes and communicate the test recipes to the host computers.20. The method of claim 1, wherein each of the test recipes comprises test parameters.21. The method of claim 20, wherein different test recipes comprise common production recipes and different test parameters.22. A method for testing memory devices, the method comprising:communicating a first test recipe from a host computer over a network to a first test site; communicating a second test recipe, different from the first test recipe, from a host computer over a network to a second test site; translating the test recipes at the respective test sites into test instructions; and testing respective memory devices at the respective test sites in accordance with the instructions. 23. The method of claim 22 wherein communicating further comprises sending the test recipe as XML formatted data.24. The method of claim 23 wherein the network comprises Ethernet.25. The method of claim 23 wherein the network comprises a local area network.26. The method of claim 23 wherein the network comprises the internet.27. The method of claim 23 wherein the network comprises a wide area network.28. The method of claim 23 wherein sending the XML formatted data further comprises sending the data using TCP/IP.29. The method of claim 23 wherein sending the XML formatted data further comprises sending the data using NFS.30. The method of claim 28 wherein the XML formatted data is downloaded from the host to the test site by FTP.31. The method of claim 22 wherein translating the test recipe further comprises:reading the test recipe with a processor at the test site; associating the recipe with instructions stored at the test site; executing the associated instructions to generate test data for storage on the memory device; reading the data from the memory device; and comparing the read data with a predetermined result to determine whether the memory device accurately stores data. 32. The method of claim 31 further comprising:formatting the results from the comparing step into XML formatted data; and sending the results to the host computer. 33. The method of claim 31 wherein the executing step comprises executing the instructions with a sequencer at the test site.34. The method of claim 31 wherein the instructions call vectors from vector memory stored at the test site.35. The method of claim 34 wherein the test data comprises address data and storage data, the address data generated algorithmically and the storage data called from vector memory.36. The method of claim 34 wherein the test data comprises address data and storage data, the storage data generated algorithmically and the address data called from vector memory.37. The method of claim 22, wherein the first test recipe is different than the second test recipe at least because the first and second test recipe comprise different test parameters.38. An apparatus for testing a memory device, the apparatus comprising:an adapter for physical interfacing with the memory device under test; a test engine interfaced with the adapter to send test data to the memory device according to test instructions and to read stored data from the memory device for comparison with predetermined results, wherein the test instructions comprise instructions to perform vector testing; and a processor interfaced with the test engine and adapted to interface with a network, the processor operable to receive a test recipe from the network and to translate the test recipe into test instructions for execution by the test engine. 39. The apparatus of claim 38, wherein the test engine comprises a sequencer.40. The apparatus of claim 38, wherein the test instructions comprise:instructions to call storage data from vector memory; and instructions to algorithmically generate address data. 41. The apparatus of claim 38, wherein the test instructions comprise:instructions to call address data from vector memory; and instructions to algorithmically generate storage data. 42. A distributed memory test system comprising:a host computer having one or more test recipes; plural test sites distributed distal from the host computer, each test site adapted to interface with a memory device under test, each test site having an embedded processor; and a network interfaced with the host computer and the plural test sites, the network communicating the test recipe from the host computer to the embedded processor for execution of the test recipe by the test site, wherein the test recipe comprises instructions for performing vector testing at the test site. 43. A method for testing memory devices, the method comprising:communicating a test recipe from a host computer over a network to a test site; translating the test recipe with a processor at the test site into test instructions; and testing a memory device at the test site in accordance with the instructions, wherein the instructions call vectors from vector memory stored at the test site. 44. The method of claim 43, further comprising:calling storage data from vector memory; and generating address data algorithmically. 45. The method of claim 43, further comprising:calling address data from vector memory; and generating storage data algorithmically.

LOADING...

이 특허에 인용된 특허 (6) 인용/피인용 타임라인 분석

Stephen Silva ; Michael Allison ; Fred Sprague ; John R. Metzner ; Thomas W. Yip ; Richard W. Gillespie, Distributed automated testing system.
상세보기
Grucci, Kyle T.; Vellayappan, Raman; Kincaid, Thomas J., Distributed component testing in an enterprise computer system.
상세보기
Dalphy, Lawrence J.; Harbert, Thomas R.; Smith, David M., Internet-implemented method supporting component repair services.
상세보기
Brehm Jeffrey A. (So. San Francisco CA) Shepherd Patrick M. (San Jose CA), Method and system for testing memory programming devices.
상세보기
Mullarkey, Patrick J.; Shore, Michael A., Method for testing a memory device having different number of data pads than the tester.
상세보기
Gross Kimberly L. (Raleigh NC) Sullivan Kirk D. (Orlando FL), Method of testing programs in a distributed environment.
상세보기

이 특허를 인용한 특허 (47) 인용/피인용 타임라인 분석

Noble, Scott; Garcia, Edward; Polyakov, Evgeny; Truebenbach, Eric L.; Merrow, Brian S., Bulk feeding disk drives to disk drive testing systems.
상세보기
Noble, Scott; Garcia, Edward; Polyakov, Evgeny; Truebenbach, Eric L.; Merrow, Brian S., Bulk feeding disk drives to disk drive testing systems.
상세보기
Truebenbach, Eric L., Bulk transfer of storage devices using manual loading.
상세보기
Truebenbach, Eric L., Bulk transfer of storage devices using manual loading.
상세보기
Martino, Peter, Damping vibrations within storage device testing systems.
상세보기
Merrow, Brian S.; Truebenbach, Eric L.; Smith, Marc Lesueur, Dependent temperature control within disk drive testing systems.
상세보기
Merrow, Brian S.; Garcia, Edward; Polyakov, Evgeny, Disk drive transport, clamping and testing.
상세보기
Merrow, Brian S.; Garcia, Edward; Polyakov, Evgeny, Disk drive transport, clamping and testing.
상세보기
Merrow, Brian S.; Garcia, Edward; Polyakov, Evgeny, Disk drive transport, clamping and testing.
상세보기
Underseth, Mark; Murphy, Dan, Dynamic interception of calls by a target device.
상세보기
Gorman, Bradley M.; McKenna, Luke R.; Woodward, Peter G., Dynamic testing of networks.
상세보기
Gorman, Bradley M.; McKenna, Luke R; Woodward, Peter G., Dynamic testing of networks.
상세보기
Xu, Kaili; Narayanan, Kaushik; Martin, Robert; Pathak, Binay, Dynamically configurable switch for distributed test lab.
상세보기
Arena, John Joseph; Suto, Anthony J., Electronic assembly test system.
상세보기
Merrow, Brian S., Enclosed operating area for disk drive testing systems.
상세보기
Merrow, Brian S., Enclosed operating area for storage device testing systems.
상세보기
Campbell, Philip; Wrinn, Joseph F., Engaging test slots.
상세보기
Avadhanam, Phani Bhushan; Hanumanthappa, Nuthan Seegehalli, Framework for testing and evaluating mobile communication devices.
상세보기
Merrow, Brian S.; Akers, Larry W., Heating storage devices in a testing system.
상세보기
Krishnaswamy, Ramachandran; Singh, Harsanjeet; Pramanick, Ankan; Elston, Mark; Chen, Leon; Adachi, Toshiaki; Tahara, Yoshihumi, Method and structure to develop a test program for semiconductor integrated circuits.
상세보기
Mandava,Ramesh Babu; Arcand,Jean Francois, Method and system for determining computer software test coverage.
상세보기
Sundararajan, Srikanth; Ho, Siu May; Shetty, Shivananda S., Method and system for storing and retrieving semiconductor tester information.
상세보기
Merrow, Brian S.; Akers, Larry W., Storage device temperature sensing.
상세보기
Merrow, Brian S.; Akers, Larry W., Storage device temperature sensing.
상세보기
Merrow, Brian S., Storage device testing system cooling.
상세보기
Merrow, Brian S., Storage device testing system cooling.
상세보기
Merrow, Brian S.; Akers, Larry W., Storage device testing system with a conductive heating assembly.
상세보기
Tsai,Hung Yuan; Xiao,San; Zeng,Ge Xin, System and method for automatically testing motherboards.
상세보기
Underseth,Mark, System and method for building a database defining a plurality of communication interfaces.
상세보기
Kaiser, Scott D.; Taylor, Randy R., System and method for distributed storage verification.
상세보기
Underseth,Mark, System and method for formatting data for transmission between an embedded computer and a host computer having different machine characteristics.
상세보기
Underseth,Mark; Fertitta,Kirk; Howell,Robert, System and method for generating data sets for testing embedded systems.
상세보기
Merrow, Brian S., Temperature control within disk drive testing systems.
상세보기
Merrow, Brian S., Temperature control within disk drive testing systems.
상세보기
Merrow, Brian S., Temperature control within storage device testing systems.
상세보기
Washizu,Nobuei, Test device and test module.
상세보기
McHardy,William Bryson; Gratias,Raymond Paul; Miller,Kevin; Nugent,Brian, Test for processor memory cache.
상세보기
Sullivan, Michael; Williamson, Jerold A., Test recipe distribution method and system.
상세보기
Merrow, Brian S.; Krikorian, Nicholas C., Test slot cooling system for a storage device testing system.
상세보기
Merrow, Brian S.; Krikorian, Nicholas C., Test slot cooling system for a storage device testing system.
상세보기
Merrow, Brian S., Thermal control system for test slot of test rack for disk drive testing system with thermoelectric device and a cooling conduit.
상세보기
Polyakov, Evgeny; Garcia, Edward; Truebenbach, Eric L.; Merrow, Brian S.; Whitaker, Brian J., Transferring disk drives within disk drive testing systems.
상세보기
Polyakov, Evgeny; Garcia, Edward; Truebenbach, Eric L.; Merrow, Brian S.; Whitaker, Brian J., Transferring disk drives within disk drive testing systems.
상세보기
Polyakov, Evgeny; Garcia, Edward; Truebenbach, Eric L.; Merrow, Brian S.; Whitaker, Brian J., Transferring storage devices within storage device testing systems.
상세보기
Toscano, John; Polyakov, Evgeny; Garcia, Edward; Truebenbach, Eric L.; Merrow, Brian S.; Whitaker, Brian J., Transferring storage devices within storage device testing systems.
상세보기
Toscano, John; Polyakov, Evgeny; Garcia, Edward; Truebenbach, Eric L.; Merrow, Brian S.; Whitaker, Brian J., Transferring storage devices within storage device testing systems.
상세보기
Merrow, Brian S., Vibration isolation within disk drive testing systems.
상세보기

활용도 분석정보

상세보기

다운로드

내보내기

활용도 Top5 특허

해당 특허가 속한 카테고리에서 활용도가 높은 상위 5개 콘텐츠를 보여줍니다.
더보기 버튼을 클릭하시면 더 많은 관련자료를 살펴볼 수 있습니다.

IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증

[미국특허] Method and system for distributed testing of electronic devices 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

이 특허에 인용된 특허 (6) 인용/피인용 타임라인 분석

이 특허를 인용한 특허 (47) 인용/피인용 타임라인 분석

활용도 분석정보

활용도 Top5 특허

관련 콘텐츠

특허 원문 보기

IPC 상위 출원인

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

선택된 텍스트

연합인증

[미국특허] Method and system for distributed testing of electronic devices 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

전체(0) 논문(0) 특허(0) 보고서(0)

전체(0) 논문(0) 특허(0) 보고서(0)

이 특허에 인용된 특허 (6) 인용/피인용 타임라인 분석

이 특허를 인용한 특허 (47) 인용/피인용 타임라인 분석

활용도 분석정보

활용도 Top5 특허 더보기

관련 콘텐츠

특허 원문 보기

IPC 상위 출원인

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

선택된 텍스트

활용도 Top5 특허