초록 ▼

A method is disclosed for forming a semiconductor wafer having a strained Si or SiGe layer on an insulator layer. The method produces a structure having a SiGe buffer layer between the insulator layer and the strained Si or SiGe layer, but eliminates the need for Si epitaxy after bonding. The method

A method is disclosed for forming a semiconductor wafer having a strained Si or SiGe layer on an insulator layer. The method produces a structure having a SiGe buffer layer between the insulator layer and the strained Si or SiGe layer, but eliminates the need for Si epitaxy after bonding. The method also eliminates interfacial contamination between strained Si and SiGe buffer layer, and allows the formation of Si/SiGe layers having a total thickness exceeding the critical thickness of the strained Si layer.

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1. A method for forming a strained Si1-yGey layer above an insulator layer, the method comprising the steps of:forming a relaxed Si1-xGex layer on a first crystalline semiconductor substrate; forming a strained Si1-yGey layer on said relaxed Si1-xGex layer; forming a Si1-zGez layer on said strained

1. A method for forming a strained Si1-yGey layer above an insulator layer, the method comprising the steps of:forming a relaxed Si1-xGex layer on a first crystalline semiconductor substrate; forming a strained Si1-yGey layer on said relaxed Si1-xGex layer; forming a Si1-zGez layer on said strained Si1-yGey layer; forming a hydrogen-rich defective layer in said relaxed Si1-xGex layer; providing a second crystalline semiconductor substrate having an insulator layer thereover; bonding a top surface of said Si1-zGez layer on said first substrate to said insulator layer on said second substrate; separating said relaxed Si1-xGex layer at said hydrogen-rich defective layer to form a structure comprising said second substrate with said insulator layer, said Si1-zGez layer on said insulator layer, said strained Si1-yGey layer on said Si1-zGez layer, and a portion of said relaxed Si1-xGex layer on said strained Si1-yGey layer; and removing said portion of said relaxed Si1-xGex layer. 2. The method of claim 1, wherein said first crystalline semiconductor substrate comprises a material selected from the group consisting of Si, SiGe, SiGeC and SiC.3. The method of claim 1, wherein said relaxed Si1-xGex layer is formed by a method comprising the steps of:growing a graded layer of SiGe; growing a constant concentration layer of SiGe on said graded layer of SiGe; and smoothing said constant concentration layer of SiGe using chemical mechanical polishing. 4. The method of claim 1, wherein said relaxed Si1-xGex layer is formed by a method comprising the steps of:growing a layer of SiGe; implanting He into the substrate with said layer of SiGe; and annealing said layer of SiGe. 5. The method of claim 1, wherein said relaxed Si1-xGex layer has a Ge concentration x of about 0.05 to about 1.0.6. The method of claim 5, wherein said relaxed Si1-xGex layer has a Ge concentration x of about 0.15 to about 0.40.7. The method of claim 1, wherein said strained Si1-yGey layer is grown epitaxially on said relaxed Si1-xGex layer.8. The method of claim 1, wherein said strained Si1-yGey layer has a Ge concentration y of 0 to 0.05.9. The method of claim 8, wherein said strained Si1-yGey layer has a Ge concentration y of 0.10. The method of claim 1, wherein said Ge concentration y is less than said Ge concentration x.11. The method of claim 1, wherein said Si1-zGez layer is grown epitaxially on said strained Si1-yGey layer.12. The method of claim 1, wherein said Si1-zGez layer has a Ge concentration z of about 0.05 to about 1.0.13. The method of claim 12, wherein said Si1-zGez layer has a Ge concentration z of about 0.10 to about 0.30.14. The method of claim 1, wherein said hydrogen-rich defective layer is formed by implanting hydrogen ions into said relaxed Si1-xGex layer.15. The method of claim 1, wherein said second crystalline semiconductor substrate comprises a material selected from the group consisting of single-crystal silicon, polysilicon, SiGe and GaAs.16. The method of claim 1, wherein said insulator layer comprises a material selected from the group consisting of silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride, hafnium oxide, zirconium oxide and doped aluminum oxide.17. The method of claim 1, further comprising, prior to said bonding step, the step of polishing the top surface of said Si1-zGez layer.18. The method of claim 1, wherein said top surface of said Si1-zGez layer is bonded to said insulator layer by a method comprising the step of:annealing at a temperature of about 50° C. to about 500° C., for a time period of about 2 hours to about 50 hours. 19. The method of claim 1, wherein said said relaxed Si1-xGex layer at said hydrogen-rich defective layer is separated by a method comprising the step of:annealing at a temperature of about 200° C. to about 600° C. 20. The method of claim 1, wherein said portion of said relaxed Si1-xGex layer is removed by a method comprising the step of:etching using hydrogen peroxide, hydrofluoric acid and acetic acid.