Variable thickness pads on a substrate surface
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-023/02
H01L-029/40
출원번호
US-0526957
(2000-03-16)
발명자
/ 주소
Sebesta, Robert David
Wilson, James Warren
출원인 / 주소
International Business Machines Corporation
대리인 / 주소
Schmeiser, Olsen &
인용정보
피인용 횟수 :
30인용 특허 :
35
초록▼
An electronic structure, and associated method of fabrication, that includes a substrate having attached circuit elements and conductive bonding pads of varying thickness. Pad categories relating to pad thickness include thick pads (17 to 50 microns), medium pads (10-17 microns), and thin pads (3 to
An electronic structure, and associated method of fabrication, that includes a substrate having attached circuit elements and conductive bonding pads of varying thickness. Pad categories relating to pad thickness include thick pads (17 to 50 microns), medium pads (10-17 microns), and thin pads (3 to 10 microns). A thick pad is used for coupling a ball grid array (BGA) to a substrate with attachment of the BGA to a circuit card. A medium pad is useful in flip-chip bonding of a chip to a substrate by use of an interfacing small solder ball. A thin copper pad, coated with a nickel-gold layer, is useful for coupling a chip to a substrate by use of a wirebond interface. The electrical structure includes an electrical coupling of two pads having different thickness, such that the pads are located either on the same surface of a substrate or on opposite sides of a substrate.
대표청구항▼
1. An electronic structure, comprising:a substrate; a first circuit line including a first portion and a second portion, wherein the second portion of the first circuit line consists of a first conductive pad, wherein the first portion of the first circuit line has a first thickness extending in a f
1. An electronic structure, comprising:a substrate; a first circuit line including a first portion and a second portion, wherein the second portion of the first circuit line consists of a first conductive pad, wherein the first portion of the first circuit line has a first thickness extending in a first direction perpendicular to a surface of the substrate, wherein the first circuit line is in direct surface-to-surface contact with the surface of the substrate, and wherein the first circuit line is totally external to an interior of the substrate, wherein a width in a second direction of the second portion of the first substrate exceeds a width in the second direction of the first portion of the first substrate, wherein the second direction is oriented parallel to the surface of the substrate; and a second circuit line including a first portion and a second portion, wherein the second portion of the second circuit line consists of a second conductive pad, wherein the first portion of the second circuit line has a second thickness extending in the first direction perpendicular to the surface of the substrate, wherein the second circuit line is in direct surface-to-surface contact with the surface of the substrate, wherein the second circuit line is electrically coupled to the first circuit line, wherein the second thickness is unequal to the first thickness, wherein the second circuit line is totally external to the interior of the substrate, and wherein the first circuit line physically touches the second circuit line in direct surface-to-surface contact, and wherein a width in the second direction of the second portion of the second substrate exceeds a width in the second direction of the first portion of the second substrate; an electronic assembly coupled to the first conductive pad; and an electronic carrier coupled to the second conductive pad. 2. The electronic structure of claim 1, wherein an end of the first circuit line includes the first conductive pad, and wherein an end of the second circuit line includes the second conductive pad.3. The electronic structure of claim 1, further comprising a protective coating that covers a portion of a circuit line, wherein the circuit line includes the first circuit line and the second circuit line.4. The electronic structure of claim 1, further comprising:a first solder ball coupling the first conductive pad to the electronic assembly; and a second solder ball coupling the second conductive pad to the electronic carrier. 5. The electronic structure of claim 4, wherein a diameter of the second solder ball is unequal to a diameter of the first solder ball.6. The electronic structure of claim 4, wherein the electronic assembly comprises a chip, and wherein the electronic carrier comprises a circuit card.7. The electronic structure of claim 1, wherein the first conductive pad includes a metallic layer, and further comprising:a first metallic coating over the metallic layer; and a second metallic coating over the first metallic coating, wherein the first metallic coating inhibits diffusion of a metal from the second metallic coating into the metallic layer. 8. The electronic structure of claim 7, further comprising:a wirebond interconnect coupled to the first conductive pad at the second metallic coating, wherein the electronic assembly is coupled to the wirebond interconnect; and a solder ball coupled to the second conductive pad, wherein the electronic carrier is coupled to the solder ball. 9. The electronic structure of claim 8, wherein the metallic layer includes copper, wherein the first metallic coating includes nickel, wherein the metal of the second metallic coating is selected from the group consisting of gold and palladium, and wherein the wirebond interconnect includes a gold wire.10. The electronic structure of claim 8, wherein the electronic assembly comprises a chip, and wherein the electronic carrier comprises a circuit card.11. An electronic structure, comprising:a substrate; a first circuit line including a first portion and a second portion, wherein the second portion of the first circuit consists of a first conductive pad, wherein the first portion of the first circuit line has a first thickness extending in a direction perpendicular to a surface of the substrate at which the first circuit line is coupled to the substrate, and wherein the first circuit line is totally external to an interior of the substrate and is in direct surface-to-surface contact with the substrate; a second circuit line including a first portion and a second portion, wherein the second portion of the second circuit line consists of a second conductive pad, wherein the first portion of the second circuit line has a second thickness extending in the direction perpendicular to the surface of the substrate at which the second circuit line is coupled to the substrate, wherein the second circuit line is electrically coupled to the first circuit line, wherein the second thickness is unequal to the first thickness, and wherein the second circuit line is totally external to the interior of the substrate and is in direct surface-to-surface contact with the substrate; and a third circuit line coupled to the substrate, wherein the third circuit line has a third thickness that is unequal to both the first thickness and the second thickness, wherein a portion of the third circuit line is electrically coupled to a portion of the first circuit line, wherein a portion of the third circuit line is electrically coupled to a portion of the second circuit line, wherein the third thickness extends in the direction perpendicular to the surface of the substrate at which the third circuit line is coupled to the substrate, wherein the third circuit line is totally external to the interior of the substrate and is in direct surface-to-surface contact with the substrate, wherein the third circuit line physically touches the first circuit line in direct surface-to-surface contact, and wherein the third circuit line physically touches the second circuit line in direct surface-to-surface contact; an electronic assembly coupled to the first conductive pad; and an electronic carrier coupled to the second conductive pad. 12. The electronic structure of claim 11, wherein the first conductive pad includes a metallic layer, and further comprising:a first metallic coating over the metallic layer; and a second metallic coating over the first metallic coating, wherein the first metallic coating inhibits diffusion of a metal from the second metallic coating into the metallic layer. 13. The electronic structure of claim 12, further comprising:a wirebond interconnect coupling the first conductive pad at the second metallic coating to the electronic assembly; and a solder ball coupling the second conductive pad to the electronic carrier. 14. The electronic structure of claim 13, wherein the electronic assembly comprises a chip, and wherein the electronic carrier comprises a circuit card.
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이 특허에 인용된 특허 (35)
Sherman John V., Arrangement of pads and through-holes for semiconductor packages.
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Frey Brenda D. (Binghamton NY) Joseph Charles A. (Candor NY) Olshefski Francis J. (Endicott NY) Wilson James W. (Vestal NY), Chip carrier with protective coating for circuitized surface.
Akram Salman (Boise ID) Farnworth Warren M. (Nampa ID) Wood Alan G. (Boise ID), Fabricating an interconnect for testing unpackaged semiconductor dice having raised bond pads.
Galvagni John L. (Colorado Springs CO) Troup Philip A. (Manitou Springs CO), High accuracy variable thickness laydown method for electronic components.
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Mahulikar Deepak (Madison CT) Hoffman Paul R. (Modesto CA) Braden Jeffrey S. (Livermore CA), Metal ball grid array package with improved thermal conductivity.
Carlos J. Sambucetti ; Daniel C. Edelstein ; John G. Gaudiello ; Judith M. Rubino ; George Walker, Method for preparing a conductive pad for electrical connection and conductive pad formed.
Contiero Claudio (Buccinasco ITX) Iannuzzi Giulio (Vimercate ITX) De Santi Giorgio (Milan ITX) Andreani Fabrizio (Parma ITX), Process for forming semiconductor device having multi-thickness metallization.
Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Muzzy, Christopher D.; Sauter, Wolfgang; Sullivan, Timothy D., Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip.
Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Muzzy, Christopher D.; Sauter, Wolfgang; Sullivan, Timothy D., Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip.
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