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Variable thickness pads on a substrate surface 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/02
  • H01L-029/40
출원번호 US-0526957 (2000-03-16)
발명자 / 주소
  • Sebesta, Robert David
  • Wilson, James Warren
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Schmeiser, Olsen &
인용정보 피인용 횟수 : 30  인용 특허 : 35

초록

An electronic structure, and associated method of fabrication, that includes a substrate having attached circuit elements and conductive bonding pads of varying thickness. Pad categories relating to pad thickness include thick pads (17 to 50 microns), medium pads (10-17 microns), and thin pads (3 to

대표청구항

1. An electronic structure, comprising:a substrate; a first circuit line including a first portion and a second portion, wherein the second portion of the first circuit line consists of a first conductive pad, wherein the first portion of the first circuit line has a first thickness extending in a f

이 특허에 인용된 특허 (35)

  1. Sherman John V., Arrangement of pads and through-holes for semiconductor packages.
  2. Barrow Michael, Ball grid array integrated circuit package that has vias located within the solder pads of a package.
  3. Higashiguchi Yutaka,JPX, Ball grid array package having electrodes on peripheral side surfaces of a package board.
  4. Lan James J. D. ; Chiang Steve S. ; Wu Paul Y. F. ; Shepherd William H. ; Xie John Y. ; Jiang Hang, Ball grid array structure and method for packaging an integrated circuit chip.
  5. Nakashima Takashi (Kitakyushu JPX), Ball grid assembly type semiconductor device having a heat diffusion function and an electric and magnetic shielding fun.
  6. Paunovic Milan (Port Washington NY) Tu King-Ning (Chappaqua NY), Barrier improvement in thin films.
  7. Lee Michael Guang-Tzong ; Beilin Solomon I. ; Wang Wen-chou Vincent, Chip and board stress relief interposer.
  8. Frey Brenda D. (Binghamton NY) Joseph Charles A. (Candor NY) Olshefski Francis J. (Endicott NY) Wilson James W. (Vestal NY), Chip carrier with protective coating for circuitized surface.
  9. M'hamed Ibnabdeljalil ; S. Leigh Phoenix, Electrical redundancy for improved mechanical reliability in ball grid array packages.
  10. Akram Salman (Boise ID) Farnworth Warren M. (Nampa ID) Wood Alan G. (Boise ID), Fabricating an interconnect for testing unpackaged semiconductor dice having raised bond pads.
  11. Brown John F. (Emmaus PA) Stanton Robert M. (Allentown PA), Fabrication of bi-level circuits.
  12. Galvagni John L. (Colorado Springs CO) Troup Philip A. (Manitou Springs CO), High accuracy variable thickness laydown method for electronic components.
  13. Bertin Claude Louis ; Ference Thomas George ; Howell Wayne John ; Sprogis Edmund Juris, Highly integrated chip-on-chip packaging.
  14. Kwon Young S. (Inchon-jikal KRX) Ahn Seung H. (Suwon KRX), J-leaded semiconductor package having a plurality of stacked ball grid array packages.
  15. Swamy N. Deepak (Austin TX), Laminated multi chip module interconnect apparatus.
  16. Cutting Lawrence R. (Owego NY) Gaynes Michael A. (Vestal NY) Johnson Eric A. (Greene NY) Milkovich Cynthia S. (Vestal NY) Perkins Jeffrey S. (Endwell NY) Pierson Mark V. (Binghamton NY) Poetzinger St, Manufacturing flexible circuit board assemblies with common heat spreaders.
  17. Mahulikar Deepak (Madison CT) Hoffman Paul R. (Modesto CA) Braden Jeffrey S. (Livermore CA), Metal ball grid array package with improved thermal conductivity.
  18. Danziger Steve M ; Shah Tushar, Method and apparatus for evaluating a known good die using both wire bond and flip-chip interconnects.
  19. Kim Jin-Sung,KRX, Method for fabricating a surface mounting type semiconductor chip package.
  20. Haji Hiroshi,JPX, Method for forming a gold plating electrode, a substrate based on the electrode forming method, and a wire bonding meth.
  21. Davis George W. ; Hurst Charles F. ; Sprauve Michael A., Method for joining rigid substrates at abutting lateral edges.
  22. Carlos J. Sambucetti ; Daniel C. Edelstein ; John G. Gaudiello ; Judith M. Rubino ; George Walker, Method for preparing a conductive pad for electrical connection and conductive pad formed.
  23. Abbott Donald C., Method to manufacture ball grid arrays with excellent solder ball adhesion for semiconductor packaging and the array.
  24. Michael W. Leddige ; Bryce D. Horine ; James A. McCall, Multi-layer printed circuit board with signal traces of varying width.
  25. Savagian Peter J. (Redondo Beach CA) Fitzhugh Thomas E. (Lomita CA), Multilayer printed wiring board with single layer vias.
  26. Matsusaka Yoshiki (Tokyo JPX) Ushiki Susumu (Tokyo JPX), Printed circuit board.
  27. Tahara Hiroshi (Osaka JPX) Kobayashi Seiju (Osaka JPX) Ohta Hitoshi (Osaka JPX), Printed circuit board having transmission lines with varying thicknesses.
  28. Contiero Claudio (Buccinasco ITX) Iannuzzi Giulio (Vimercate ITX) De Santi Giorgio (Milan ITX) Andreani Fabrizio (Parma ITX), Process for forming semiconductor device having multi-thickness metallization.
  29. King Jerrold L. (Boise ID) Brooks Jerry M. (Caldwell ID), Semiconductor chip package.
  30. Murakami Gen,JPX ; Mita Mamoru,JPX ; Kumakura Toyohiko,JPX ; Okabe Norio,JPX ; Komatsu Katsuji,JPX ; Shinzawa Shoji,JPX, Semiconductor device, interposer for semiconductor device.
  31. Warwick William Arthur (Winchester EN), Semiconductor integrated circuit devices.
  32. Murata Masaomi (Chiba JPX), Semiconductor integrated circuit provided with contact for inter-layer connection and method of inter-layer connection t.
  33. Akram, Salman; Brooks, Jerry M., Semiconductor package with stacked substrates and multiple semiconductor dice.
  34. Akram Salman ; Wood Alan G. ; Farnworth Warren M., Single piece package for semiconductor die.
  35. Nishiguchi Masanori (Yokohama JPX) Miki Atsushi (Yokohama JPX), Substrate for packaging a semiconductor device.

이 특허를 인용한 특허 (30)

  1. Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Muzzy, Christopher D.; Sauter, Wolfgang; Sullivan, Timothy D., Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip.
  2. Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Muzzy, Christopher D.; Sauter, Wolfgang; Sullivan, Timothy D., Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip.
  3. Gambino, Jeffrey P.; Graf, Richard S.; Leidy, Robert K.; Maling, Jeffrey C., Dual bond pad structure for photonics.
  4. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation structure for semiconductor chip or wafer.
  5. Oh, Yun-jin, Semiconductor package and method of manufacturing the same.
  6. Guerin, Luc; Interrante, Mario J.; Shapiro, Michael J.; Tran-Quinn, Thuy; Truong, Van T., Solder ball contact susceptible to lower stress.
  7. Guerin, Luc; Interrante, Mario J.; Shapiro, Michael J.; Tran-Quinn, Thuy; Truong, Van T., Solder ball contact susceptible to lower stress.
  8. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  9. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  10. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  11. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  12. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  13. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  14. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  15. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  16. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  17. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  18. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  19. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  20. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  21. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  22. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  23. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  24. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  25. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  26. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  27. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  28. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  29. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  30. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
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