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Method of forming strained silicon on insulator substrate 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H10L-021/20
  • H10L-021/36
출원번호 US-0379873 (2003-03-05)
발명자 / 주소
  • Yeo, Yee-Chia
  • Lee, Wen-Chin
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, Ltd.
대리인 / 주소
    Slater &
인용정보 피인용 횟수 : 37  인용 특허 : 43

초록

A method of forming a strained-silicon-on-insulator substrate is disclosed. A target wafer includes an insulator layer on a substrate. A donor wafer includes a bulk semiconductor substrate having a lattice constant different from a lattice constant of silicon and a strained silicon layer formed on t

대표청구항

1. A method of forming a strained-silicon-on-insulator substrate comprising the steps of:providing a bulk semiconductor substrate, the bulk semiconductor substrate having a lattice constant different from a lattice constant of silicon; forming a strained silicon layer on the bulk semiconductor subst

이 특허에 인용된 특허 (43)

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  12. Kern Rim, Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation.
  13. Maa, Jer-Shen; Tweet, Douglas J.; Hsu, Sheng Teng; Lee, Jong-Jan, Molecular hydrogen implantation method for forming a relaxed silicon germanium layer with high germanium content.
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  17. Alexander Yuri Usenko, Process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate.
  18. Sakaguchi, Kiyofumi; Yonehara, Takao; Nishida, Shoji; Yamagata, Kenji, Process for producing semiconductor article.
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  25. Kunikiyo, Tatsuya, Semiconductor device and SOI substrate.
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  29. Yamauchi, Shoichi; Ohshima, Hisayoshi; Matsui, Masaki; Onoda, Kunihiro; Ooka, Tadao; Yamanaka, Akitoshi; Izumi, Toshifumi, Semiconductor substrate and method of manufacturing the same.
  30. Hause Fred N. ; Dawson Robert ; May Charles E. ; Gardner Mark I. ; Chang Kuang-Yeh, Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties.
  31. Qi Xiang, Semiconductor-on-insulator device with nitrided buried oxide and method of fabricating.
  32. Helmut Puchner, Silicon carbide CMOS channel.
  33. Clifton G. Fonstad, Jr. ; Joanna M. London ; Joseph F. Ahadian, Silicon on III-V semiconductor bonding for monolithic optoelectronic integration.
  34. Ipri ; Alfred C., Silicon resistive device for integrated circuits.
  35. Bliss David F. ; Demczyk Brian G. ; Bailey John, Silicon-germanium bulk alloy growth by liquid encapsulated zone melting.
  36. Henley Francois J. ; Cheung Nathan W., Silicon-on-silicon wafer bonding process using a thin film blister-separation method.
  37. Behfar Alex A. ; Srikrishnan Kris V., Simultaneous multiple silicon on insulator (SOI) wafer production.
  38. Srikrishnan Kris V., Smart-cut process for the production of thin semiconductor material films.
  39. McKee Rodney Allen ; Walker Frederick Joseph, Strain-based control of crystal anisotropy for perovskite oxides on semiconductor-based material.
  40. Chu, Jack O.; Ismail, Khaled, Strained Si based layer made by UHV-CVD, and devices therein.
  41. Rim, Kern, Strained silicon on insulator structures.
  42. Hommei Takao (Hitachinaka JPX) Takuma Yutaka (Tokyo JPX) Takeshima Hirotaka (Ryugasaki JPX) Takeuchi Hiroyuki (Kashiwa JPX) Miyamoto Yoshiyuki (Abiko JPX) Fukutomi Kiyoshi (Tokyo JPX) Kawano Hajime (, Superconducting magnet apparatus using superconducting multilayer composite member, method of magnetizing the same and m.
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이 특허를 인용한 특허 (37)

  1. Forbes, Leonard, Bonded strained semiconductor with a desired surface orientation and conductance direction.
  2. Bu, Haowen; Yu, Shaofeng; Pinto, Angelo; Varghese, Ajith, Border region defect reduction in hybrid orientation technology (HOT) direct silicon bonded (DSB) substrates.
  3. Chen, Tze-Chiang; Ieong, Meikei; Jammy, Rajarao; Khare, Mukesh V.; Sung, Chun-yung; Wise, Richard; Yan, Hongwen; Zhang, Ying, CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials.
  4. Chen, Tze-Chiang; Ieong, Meikei; Jammy, Rajarao; Khare, Mukesh V.; Sung, Chun-yung; Wise, Richard; Yan, Hongwen; Zhang, Ying, CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials.
  5. Chen, Tze-Chiang; Ieong, Meikei; Jammy, Rajarao; Khare, Mukesh V.; Sung, Chun-yung; Wise, Richard; Yan, Hongwen; Zhang, Ying, CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials.
  6. Yaocheng, Liu; Donaton, Ricardo A.; Rim, Kern, CMOS structure including differential channel stressing layer compositions.
  7. Bedell, Stephen W.; Cheng, Kangguo; Khakifirooz, Ali; Kulkarni, Pranita, Enhancement of charge carrier mobility in transistors.
  8. Bedell, Stephen W.; Cheng, Kangguo; Khakifirooz, Ali; Kulkarni, Pranita, Enhancement of charge carrier mobility in transistors.
  9. Bedell, Stephen W.; Cohen, Stephan A.; de Souza, Joel P.; Nummy, Karen A.; Poindexter, Daniel J.; Sadana, Devendra K., Enhancing robustness of SOI substrate containing a buried N+ silicon layer for CMOS processing.
  10. Bhattacharyya, Arup; Forbes, Leonard; Farrar, Paul A, Implantation processes for straining transistor channels of semiconductor device structures and semiconductor devices with strained transistor channels.
  11. Forbes, Leonard, Localized compressive strained semiconductor.
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  15. Forbes, Leonard, Methods for fabricating semiconductor device structures.
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  18. Liu, Zongrong; Wang, Lei, Micrometer scale components.
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  20. Furukawa, Toshiharu; Horak, David V.; Koburger, III, Charles W.; Shi, Leathen, Multiple layer and crystal plane orientation semiconductor substrate.
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  22. Forbes, Leonard; Ahn, Kie Y.; Reinberg, Alan R., Non-volatile memory device with tensile strained silicon layer.
  23. Huang, Yu-Lien; Fan, Chun-Hsiang; Li, Yung-Ta, Quantum well fin-like field effect transistor (QWFinFET) having a two-section combo QW structure.
  24. Huang, Yu-Lien; Fan, Chun-Hsiang; Li, Yung-Ta, Quantum well fin-like field effect transistor (QWFinFET) having a two-section combo QW structure.
  25. Yeo,Yee Chia; Hu,Chenming, SOI chip with recess-resistant buried insulator and method of manufacturing the same.
  26. Wise, Rick L.; Pinto, Angelo, Semiconductor device made by the method of producing hybrid orientnation (100) strained silicon with (110) silicon.
  27. Bhattacharyya, Arup; Forbes, Leonard; Farrar, Paul A., Semiconductor device structures including strained transistor channels.
  28. Sinha, Nishant; Sandhu, Gurtej S.; Smythe, John, Semiconductor material manufacture.
  29. Yamazaki, Shunpei; Ichijo, Mitsuhiro; Furuno, Makoto; Ohtsuki, Takashi; Okazaki, Kenichi; Tanaka, Tetsuhiro; Yasumoto, Seiji, Semiconductor substrate and manufacturing method of semiconductor device.
  30. Chou, Anthony I.; Furukawa, Toshiharu; Haensch, Wilfried; Ren, Zhibin; Singh, Dinkar V.; Sleight, Jeffrey W., Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX).
  31. Waite, Andrew Michael; Lunning, Scott, Strained MOS device and methods for its fabrication.
  32. Cheng, Kangguo; Doris, Bruce B.; Hashemi, Pouya; Khakifirooz, Ali, Strained silicon and strained silicon germanium on insulator metal oxide semiconductor field effect transistors (MOSFETs).
  33. Bryant, Andres; Ouyang, Qiqing; Rim, Kern, Strained-silicon CMOS device and method.
  34. Bryant,Andres; Ouyang,Qiqing; Rim,Kern, Strained-silicon CMOS device and method.
  35. Wei,Andy; Kammler,Thorsten; Raab,Michael; Horstmann,Manfred, Technique for forming a substrate having crystalline semiconductor regions of different characteristics located above a crystalline bulk substrate.
  36. Wei, Andy; Kammler, Thorsten; Boschke, Roman; Horstmann, Manfred, Transistor with embedded silicon/germanium material on a strained semiconductor on insulator substrate.
  37. Ieong,Meikei; Yang,Min, Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations.
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