이 특허에 인용된 특허 (40)

1. Furukawa, Toshiharu; Hakey, Mark C.; Holmes, Steven J.; Horak, David V.; Rabidoux, Paul A., Borderless gate structures.

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2. Trivedi, Jigish D.; Wang, Zhongze; Abbott, Todd R.; Cho, Chih-Chen, Cross-diffusion resistant dual-polycide semiconductor structure and method.

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3. Trivedi, Jigish D.; Wang, Zhongze; Abbott, Todd R.; Cho, Chih-Chen, Cross-diffusion resistant dual-polycide semiconductor structure and method.

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4. Sun Sey-Ping ; Gardner Mark I. ; Ngo Minh Van, In-situ SiON deposition/bake/TEOS deposition process for reduction of defects in interlevel dielectric for integrated circuit interconnects.

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5. Manning H. Montgomery, Integrated circuitry, methods of fabricating integrated circuitry, methods of forming local interconnects, and methods of forming conductive lines.

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6. Todd R. Abbott ; Michael P. Violette ; Charles H. Dennison, METHOD OF FORMING A LOCAL INTERCONNECT, METHOD OF FABRICATING INTEGRATED CIRCUITRY COMPRISING AN SRAM CELL HAVING A LOCAL INTERCONNECT AND HAVING CIRCUITRY PERIPHERAL TO THE SRAM CELL, AND METHOD OF .

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7. Nulty James E. ; Petti Christopher J., Method for eliminating lateral spacer erosion on enclosed contact topographies during RF sputter cleaning.

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8. Furukawa Toshiharu ; Hakey Mark C. ; Holmes Steven J. ; Horak David V. ; Rabidoux Paul A., Method for forming borderless gate structures and apparatus formed thereby.

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9. YongZhong Hu ; Fei Wang ; Wenge Yang ; Yu Sun ; Ramkumar Subramanian, Method for forming self-aligned contacts and local interconnects using decoupled local interconnect process.

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10. Kinoshita Hiroyuki ; Hu YongZhong ; Sun Yu ; Wang Fei, Method for forming self-aligned contacts and local interconnects using self-aligned local interconnects.

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11. Wong Siu-Weng S. (Ithaca NY) Chen Devereaux C. (San Jose CA) Chiu Kuang-Yi (Los Altos Hills CA), Method for making silicide interconnection structures for integrated circuit devices.

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12. Hsu Sheng Teng, Method for manufacturing a CMOS self-aligned strapped interconnection.

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13. Nagashima Naoki,JPX, Method of fabricating semiconductor device.

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14. Li Li ; Hu Yongjun Jeff, Method of forming a conductive line and method of forming a local interconnect.

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15. Abbott, Todd R.; Wang, Zhongze; Trivedi, Jigish D.; Cho, Chih-Chen, Method of forming a field effect transistor.

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16. Ngo Minh Van ; Besser Paul R. ; Liu Yowjuang Bill, Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide.

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17. Mark Fischer ; Jigish D. Trivedi ; Charles H. Dennison ; Todd R. Abbott ; Raymond A. Turi, Method of forming plugs and local interconnect for embedded memory/system-on-chip (SOC) applications.

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18. Chen Min-Liang (Allentown PA), Method of making electrical contacts to gate structures in integrated circuits.

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19. Abbott, Todd; Trivedi, Jigish D.; Violette, Mike; Dennison, Chuck, Method of selectively forming local interconnects using design rules.

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20. Abbott, Todd; Trivedi, Jigish D.; Violette, Mike; Dennison, Chuck, Method of selectively forming local interconnects using design rules.

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21. Foote David K. ; Ngo Minh Van ; Chan Darin A., Methods for making a semiconductor device with improved hot carrier lifetime.

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22. Cho, Chih-Chen; Wang, Zhongze, Methods for making semiconductor structures having high-speed areas and high-density areas.

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23. Abbott Todd R. ; Violette Michael P. ; Dennison Charles H., Methods of forming a local interconnect method of fabricating integrated circuitry comprising an SRAM cell having a local interconnect and having circuitry peripheral to the SRAM cell and method of f.

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24. Verrett Douglas P. (Sugarland TX), Polycide local interconnect method and structure.

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25. Lage Craig S. ; Bhat Mousumi ; Lii Yeong-Jyh Tom ; Nagy Andrew G. ; Frisa Larry E.,DEX ; Filipiak Stanley M. ; O'Meara David L. ; Ong T. P. ; Woo Michael P. ; Sparks Terry G. ; Gelatos Carol M., Process for forming a semiconductor device having an interconnect or conductive film electrically insulated from a conductive member or region.

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26. Jin, Bo, SRAM cell design.

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27. O'Brien Sean ; Prinslow Douglas A., Self-aligned silicide process.

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28. Wieczorek Karsen ; Hause Frederick N., Semiconductor device having elevated silicidation layer and process for fabrication thereof.

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29. Kaoru Mikagi JP, Semiconductor device having silicide films on a gate electrode and a diffusion layer and manufacturing method thereof.

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30. Kimura Masatoshi,JPX, Semiconductor device with particular silicide structure.

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31. Lage, Craig S.; Bhat, Mousumi; Lii, Yeong-Jyh Tom; Nagy, Andrew G.; Frisa, Larry E.; Filipiak, Stanley M.; O'Meara, David L.; Ong, T. P.; Woo, Michael P.; Sparks, Terry G.; Gelatos, Carol M., Semiconductor device, memory cell, and processes for forming them.

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32. Hu Yongjun Jeff, Semiconductor processing method of forming a high purity <200> grain orientation tin layer and semiconductor processing method of forming a conductive interconnect line.

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33. Bo Jin ; Jianmin Qiao, Semiconductor structure and method of making contacts and source and/or drain junctions in a semiconductor device.

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34. Trivedi, Jigish D.; Abbott, Todd R.; Wang, Zhongze, Sidewall strap for complementary semiconductor structures and method of making same.

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35. En William G. ; Ngo Minh Van ; Yang Chih-Yuh ; Foote David K. ; Bell Scott A. ; Karlsson Olov B. ; Lyons Christopher F., Silicon oxime spacer for preventing over-etching during local interconnect formation.

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36. Nulty, James E.; Petti, Christopher J., Structure having reduced lateral spacer erosion.

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37. Gualandris Fabio,ITX ; Maggis Aldo,ITX, Surface field effect transistor with depressed source and/or drain areas for ULSI integrated devices.

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38. Shepela Adam ; Grula Gregory J. ; Zetterlund Bjorn, Transistor fabrication process in which a contact metallization is formed with different silicide thickness over gate interconnect material and transistor source/drain regions.

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39. Li Weidan ; Yeh Wen-Chin ; Rakkhit Rajat, Tungsten local interconnect for silicon integrated circuit structures, and method of making same.

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40. Liaw Jhon-Jhy,TWX, Tungsten local interconnect, using a silicon nitride capped self-aligned contact process.

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