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Methods and apparatus for inbound PCI configuration cycles are disclosed. By definition, PCI bridges block upstream progress of configuration cycles initiated by a PCI bus master on their secondary buses. In the described embodiments, a PCI bus master can execute a configuration cycle despite this l

Methods and apparatus for inbound PCI configuration cycles are disclosed. By definition, PCI bridges block upstream progress of configuration cycles initiated by a PCI bus master on their secondary buses. In the described embodiments, a PCI bus master can execute a configuration cycle despite this limitation, by converting the configuration cycle command to Memory Read and Write commands that a PCI bridge will forward upstream. The PCI bus master writes the address of a target configuration register to a first predefined address, and pushes or pulls data from that target register by subsequently initiating a memory access to a second predefined address. A platform chipset is designed to recognize Memory Read and Write accesses to the predefined addresses as relating to an inbound configuration cycle. When a memory access to the second address is received, the chipset uses the information stored at the first address to form and execute a configuration cycle on behalf of the downstream PCI bus master.

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1. A method of operating a computer system having a bus slot in at least one local bus, a chipset, and at least one configuration register addressable by the chipset, the method comprising:connecting a first bus agent to the local bus via a local bus card inserted in the bus slot; the bus agent writ

1. A method of operating a computer system having a bus slot in at least one local bus, a chipset, and at least one configuration register addressable by the chipset, the method comprising:connecting a first bus agent to the local bus via a local bus card inserted in the bus slot; the bus agent writing first data to a first predefined memory address using a local bus write command, the first data describing the location of the at least one configuration register; the chipset routing the first data, based on the first predefined memory address, to an inbound configuration address register; the bus agent initiating a local bus memory access command to a second predefined memory address; and the chipset responding, based on the second predefined memory address, to the memory access command by initiating a configuration cycle using the first data to form a configuration cycle address. 2. The method of claim 1, wherein the local bus memory access command is a memory write command comprising an address phase, supplying the second predefined memory address, and a data phase, supplying data to be written in the at least one configuration register, the chipset initiating a configuration cycle comprising accepting the data supplied during the data phase and writing the accepted data to the at least one configuration register as part of a configuration write cycle issued by the chipset as bus master.3. The method of claim 1, wherein the local bus memory access command is a memory read command, the chipset responding to the memory read command by:instructing the bus agent to retry the memory read command later; initiating the configuration cycle by reading configuration register data from the configuration register indicated in the inbound configuration address register; and holding the read configuration register data and waiting for the bus agent to retry the memory read command. 4. The method of claim 3, further comprising the bus agent retrying the memory read command, and the chipset supplying the read configuration register data to the bus agent in response to the retried memory command.5. The method of claim 1, wherein the first and second predefined memory addresses exist within a memory area mapped to the chipset, the chipset detecting the presence of the first or second predefined memory addresses in local bus commands by screening those commands for addresses within that memory area.6. The method of claim 1, wherein the configuration register exists within a component of the chipset, the chipset using its internal data paths to access the at least one configuration register.7. The method of claim 1, wherein the at least one configuration register exists within a second bus agent on a second local bus separate from the local bus connected to the first bus agent, the chipset initiating a configuration cycle comprising issuing a local bus configuration access command on the second local bus.8. A method of accessing the platform configuration registers of a first computer system from a second computer system, wherein the first computer system has at least one chipset-connected local bus having at bus slot, the method comprising:connecting the second computer system to the first computer system through a local bus card inserted in the bus slot; and instructing the local bus card, from the second computer system, to supply a request to the first computer system chipset for access to a platform configuration register, the request comprising issuing local bus memory access commands to specific memory addresses that the chipset recognizes as reserved for triggering chipset-initiated configuration cycles. 9. The method of claim 8, wherein the request for access to a platform configuration register comprises a request to read the contents of a platform configuration register, the method further comprising the local bus card receiving data, in the form of memory read command data, from the chipset, the memory read command data comprising the contents of the platform configuration register, and the local bus card forwarding the data to the second computer system.10. The method of claim 8, wherein at the time of instructing the local bus card, the platform of the first computer system is powered but not under the control of a first computer system host processor.11. A method of managing a computer system platform from a management processor separate from the computer system host processor, wherein the computer system has at least one chipset-connected local bus having a bus slot, the method comprising:interfacing the management processor with the computer system platform through a local bus card inserted in the bus slot; and operating the local bus card as a bus master to supply a request to the computer system chipset for access to a platform configuration register, the request comprising issuing local bus memory access commands to specific memory addresses that the chipset recognizes as reserved for triggering chipset-initiated configuration cycles. 12. The method of claim 11, wherein operating the local bus card as a bus master comprises the management processor periodically requesting that the chipset supply, through the local bus card, the contents of a set of platform configuration registers capable of storing platform error information.13. The method of claim 12, wherein when the chipset supplies the contents of a platform configuration register capable of storing platform error information, the method further comprises the management processor evaluating those contents for error indications, and responding to an affirmative error indication by attempting to reconfigure the computer system.14. The method of claim 13, wherein attempting to reconfigure the computer system comprises disabling an input/output subsystem of the platform.15. The method of claim 13, wherein attempting to reconfigure the computer system comprises interrupting a computer system host processor to respond to the error.16. A computer chipset comprising:a local bus controller to interface with local bus agents connected to the controller through at least one local bus connection point; an inbound configuration address register to store addressing information for a configuration cycle; a configuration cycle command generator capable of initiating a configuration cycle, the configuration cycle targeting a configuration register specified by the contents of the inbound configuration address register; and an address decoder/router to decode command addresses received from local bus agents through the local bus controller, the decoder having the capability to recognize a memory write command with a first memory address as a write to the inbound configuration address register and route write command data to that register, the decoder having the capability to recognize a memory access command with a second memory address as a request for the chipset to perform a configuration cycle, and route a signal to the configuration cycle command generator to initiate a configuration cycle, said local bus controller, inbound configuration address register, configuration cycle command generator, and address decoder/router intergrated in a first circuit, the chipset comprising at least two instances of the first circuit, each capable of interfacing as claimed with local bus agents connected to that circuit local bus controller. 17. The chipset of claim 16, comprising multiple interconnectable chipset integrated circuits, each having a configuration register set, the configuration cycle command generator capable of accessing the configuration register set of an integrated circuit, other than the circuit upon which that command generator is integrated, during a configuration cycle requested through the address decoder/router.18. The chipset of claim 17, wherein, for each chipset integrated circuit including a configuration register set, that register set is addressable using configuration addresses compatible with local bus configuration register set addressing.19. The chipset of claim 16, further comprising an inbound configuration data register capable of holding data associated with the second memory address, the chipset capable of storing, in the inbound configuration data register, data supplied as a result of a configuration road cycle initiated by the configuration cycle command generator.20. The chipset of claim 19, the address decoder/router having the capability to recognize a retry of a memory read command to the second memory address, and cause the local bus controller to supply, on the local bus and as the result of the retried memory read command, data held in the inbound configuration data register.21. The chipset of claim 16, each instance of the first circuit having the capability to initiate configuration cycles to local bus agents connected to another instance of the first circuit.22. A computer system comprisingat least one local bus capable of supporting multiple bus agents on at least one local bus card; at least one bus slot in said local bus, said local bus card being received in said slot; and a chipset connected to the at least one local bus, having the capability to: detect a memory access command initiated by a bus agent on said local bus card to a predefined memory address as a request to perform a configuration cycle on behalf of that bus agent; and perform the requested configuration cycle on behalf of that bus agent. 23. The computer system of claim 22, wherein the at least one local bus comprises at least two disjoint local buses, the chipset having the capability to execute a configuration cycle on one local bus at the request of a bus agent on the other local bus.24. The computer system of claim 22, wherein the chipset comprises multiple interconnected integrated circuits each having a configuration register set, the chipset having the capability to execute a configuration cycle to a configuration register set on any of the multiple interconnected integrated circuits on behalf of the bus agent.25. A local bus card comprising:a local bus master interface; and a configuration cycle initiator capable of converting a local bus configuration access command to at least two local bus memory access commands, the first command utilizing the bus master interface to perform a memory write to a first predefined memory address, the memory write data encoding a configuration register address description for the local bus configuration access command, the second command utilizing the bus master interface to perform a memory access to a second predefined memory address. 26. The local bus card of claim 25, the configuration cycle initiator capable of causing the local bus master interface to supply to an attached local bus, when the configuration access command is a configuration write command, configuration register write data during the data phase of the second command.27. The local bus card of claim 25, the configuration cycle initiator capable of returning, when the configuration access command is a configuration read command, data received by the local bus master interface from the attached local bus during the data phase of the second command, as the results of the configuration access command.