IPC분류정보
| 국가/구분 |
United States(US) Patent
등록
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| 국제특허분류(IPC7판) |
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| 출원번호 |
US-0178103
(2002-06-24)
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발명자
/ 주소 |
- Mok, Sammy
- Chong, Fu Chiung
- Swiatowiec, Frank John
- Lahiri, Syamal Kumar
- Haemer, Joseph Michael
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| 출원인 / 주소 |
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| 대리인 / 주소 |
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| 인용정보 |
피인용 횟수 :
108 인용 특허 :
10 |
초록
▼
Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semicondu
Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates. Alternate card assembly structures comprise a compliant carrier structure, such as a decal or screen, which is adhesively attached to the probe chip substrate.
대표청구항
▼
1. A test apparatus for an integrated circuit wafer, comprising:a motherboard substrate having a bottom surface and a top surface, and a plurality of electrical conductors extending from the bottom surface to the top surface; a probe chip substrate comprising a probe surface and a connector surface,
1. A test apparatus for an integrated circuit wafer, comprising:a motherboard substrate having a bottom surface and a top surface, and a plurality of electrical conductors extending from the bottom surface to the top surface; a probe chip substrate comprising a probe surface and a connector surface, a plurality of probe springs on the probe surface; a plurality of electrical contacts on the connector surface, and a plurality of probe chip electrical connections, wherein each of the probe springs is electrically connected to at least one contact through at least one probe chip electrical connection; at least one intermediate connector located between the motherboard substrate and the probe chip substrate, the intermediate connector comprising at least one electrically conductive connection between each of the plurality of electrical contacts on the probe chip substrate and each of the electrical conductors on the bottom surface of the motherboard substrate; and a probe chip carrier attached in relation to the motherboard substrate, the probe chip carrier comprising a compliant member where in the compliant member is attached to the connector surface of the probe chip substrate; wherein the probe chip substrate is supported by the compliant member relative to the motherboard. 2. The test apparatus of claim 1, wherein the plurality of probe springs comprise a fixed portion attached to the probe chip substrate and a free portion, initially attached to the probe chip substrate, which upon release, extend away from the probe chip substrate as a result of an inherent stress gradient.3. The test apparatus of claim 2, wherein the plurality of probe springs each comprise a plurality of layers, and wherein the free portions of probe springs extend away upon release from the probe chip substrate as a result of the inherent stress gradient defined between the plurality of layers.4. The test apparatus of claim 2, wherein the plurality of probe springs are sputter formed.5. The test apparatus of claim 2, wherein the plurality of probe springs are plateably formed.6. The test apparatus of claim 2, wherein said plurality of probe springs are photolithographically patterned springs, in which the free portions define a three-dimensional structure.7. The test apparatus of claim 1, wherein at least one of the electrical connections comprises a plurality of electrically conductive vias.8. The test apparatus of claim 1, wherein the compliant member is attached to the connector surface of the probe chip substrate.9. The test apparatus of claim 1, further comprising:a stiffener plate fixedly attached to the top surface of the motherboard substrate. 10. The test apparatus of claim 9, wherein the stiffener plate comprises a rigid material.11. The test apparatus of claim 9, wherein the stiffener plate comprises stainless steel.12. The test apparatus of claim 9, wherein at least one component recess is defined in the stiffener plate proximate the top surface of the motherboard substrate, and wherein the apparatus further comprises:at least one component extending from the motherboard substrate within the component recess. 13. The test apparatus of claim 12, wherein the component is a capacitor.14. The test apparatus of claim 1, wherein the probe chip substrate comprises an inner region and an outer peripheral region, and wherein the compliant member is attached to the peripheral region of the probe chip substrate.15. The test apparatus of claim 1, wherein the probe chip substrate comprises an inner region and an outer peripheral region, and wherein the compliant member is adhesively attached to the peripheral region of the probe chip substrate.16. The test apparatus of claim 1, wherein the compliant member is a film.17. The test apparatus of claim 16, wherein the film comprises polyimide.18. The test apparatus of claim 16, wherein the probe chip comprises an outer periphery, and wherein the film is attached about the outer periphery.19. The test apparatus of claim 1, wherein the compliant member is a screen.20. The test apparatus of claim 1, wherein the compliant member is a mesh.21. The test apparatus of claim 1, wherein the compliant member comprises KAPTON™.22. The test apparatus of claim 1, wherein the intermediate connector comprises an interposer having a first plurality of compliant electrical contacts on a first surface and a second plurality of compliant electrical contacts on a second surface opposite the first surface.23. The test apparatus of claim 1, further comprising: a permanent electrical interface between the intermediate connector and the motherboard substrate.24. The test apparatus of claim 23, wherein the permanent interface comprises a solder ball array.25. The test apparatus of claim 23, wherein the permanent interface comprises an anisotropic conductive film.26. The test apparatus of claim 23, wherein the permanent interface comprises a plurality of electrically conductive pins.27. The test apparatus of claim 1, further comprising:at least one standoff fixedly attached to the probe surface of the probe chip substrate. 28. The test apparatus of claim 1, further comprising:at least one standoff fixedly attached to the connector surface of the probe chip substrate. 29. The test apparatus of claim 1, further comprising:at least one passive component incorporated as an assembled component on the probe chip substrate. 30. The test apparatus of claim 29, wherein the passive component is mounted on the connector surface of the probe chip substrate.31. The test apparatus of claim 29, wherein the passive component is a capacitor.32. The test apparatus of claim 29, wherein the capacitor is a decoupling capacitor.33. The test apparatus of claim 29, wherein the passive component is a resistor.34. The test apparatus of claim 29, wherein the passive component is an inductor.35. The test apparatus of claim 1, further comprising:at least one capacitor fabricated on the probe chip substrate. 36. The apparatus of claim 1, wherein at least one of the substrates is comprised of silicon, and further comprising:at least one capacitor fabricated within at least one of the substrates. 37. The test apparatus of claim 1, further comprising:a planarity adjustment mechanism in which the planarity of the probe chip is adjustable relative to the motherboard substrate. 38. The test apparatus of claim 1, wherein the intermediate connector comprises a printed wiring board, and wherein the plurality of electrically conductive connections comprise vias having means for electrical connection to the probe chip and means for electrical connection to the motherboard.39. The test apparatus of claim 38, wherein the means for electrical connection to the motherboard comprises an interposer.40. The test apparatus of claim 38, wherein the means for electrical connection to the probe chip comprises an interposer.41. The test apparatus of claim 1, wherein the intermediate connector comprises a Z-block, comprising a vertical translation substrate having a lower surface and an upper surface, and a plurality of electrically conductive connections which extend from the lower surface to the upper surface thereof, each of the electrically conductive connections comprising at least one electrically conductive via.42. The test apparatus of claim 41, further comprising an interposer between the Z-block and the motherboard substrate.43. The test apparatus of claim 41, further comprising an interposer between the Z-block and the probe chip substrate.44. The test apparatus of claim 1, wherein the probe chip substrate comprises a plurality of holes defined therethrough between the probe surface and the connector surface, and wherein each of the plurality of probe chip electrical connections are electrically conductive vias located within each of the plurality, of holes in the probe chip substrate.45. The test apparatus of claim 1, wherein the probe chip substrate comprises an electrically insulative material.46. The test apparatus of claim 1, wherein the probe chip substrate comprises a dielectric material.47. The test apparatus of claim 1, wherein the probe chip substrate comprises an electrically conductive material.48. The test apparatus of claim 1, further comprising: at least one bypass capacitor electrically connected to at least one of the plurality of electrical connections on the probe chip substrate.49. The test apparatus of claim 1, wherein the intermediate connector comprises an electrically conductive pin block having a plurality of holes defined between a lower surface and an upper surface thereof, and wherein the plurality of electrically conductive connections comprise pins extending through the plurality of holes, the pins comprising means for connection to the probe chip and means for connection to the motherboard.50. The test apparatus of claim 49, further comprising:dielectric within the plurality of holes. 51. The test apparatus of claim 49, further comprising:an electrically conductive ground contact between at least one of the pins and the pin block. 52. The test apparatus of claim 49, further comprising:a zero activation force (ZIF) actuation template located between the metal pin block and the motherboard. 53. The test apparatus of claim 49, further comprising:a lower pin template located on the lower surface of the pin block, in which the pins extend through the lower pin template. 54. The test apparatus of claim 53, wherein the lower pin template comprises KAPTON™.55. The test apparatus of claim 49, further comprising:an upper pin template located on the upper surface of the pin block, in which the pins extend through the upper pin template. 56. The test apparatus of claim 55, wherein the upper pin template comprises KAPTON™.57. The test apparatus of claim 49, wherein the means for electrical connection to the probe chip comprises a solder bell array.58. The test apparatus of claim 49, wherein the means for electrical connection to the probe chip comprises solder joints.59. The teat apparatus of claim 49, wherein the means for electrical connection to the motherboard comprises a pin grid array.60. The test apparatus of claim 49, wherein the means for electrical connection to the probe chip comprises a plurality of springs.61. The test apparatus of claim 49, wherein the means for electrical connection to the motherboard comprises a pin socket array in the motherboard.62. The test apparatus of claim 49, wherein the means for electrical connection to the motherboard comprises solder joints.63. The test apparatus of claim 49, wherein the means for electrical connection to the motherboard comprises press fit pin connections.64. The test apparatus of claim 1, wherein the motherboard substrate further comprises at least one electrically conducting path with matched impedance.65. The test apparatus of claim 1, wherein the intermediate connector further comprises at least one electrically conducting path with matched impedance.66. The test apparatus of claim 1, wherein the probe chip substrate further comprises at least one electrically conducting path with matched impedance.67. The test apparatus of claim 1, further comprising:at least one electrically conducting path with matched impedance extending from the top surface of the motherboard substrate to the probe surface of the probe chip substrate.
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