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특허 상세정보

Remote translation mechanism for a multi-node system

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G06F-012/10   
미국특허분류(USC) 711/202; 711/205; 711/207; 711/220; 711/221; 370/395.3; 370/395.31; 370/389
출원번호 US-0235898 (2002-09-04)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Schwegman, Lundberg, Woessner &
인용정보 피인용 횟수 : 26  인용 특허 : 7
초록

A remote translation mechanism for a multi-node system. One embodiment of the invention provides a method for remotely translating a virtual memory address into a physical memory address in a multi-node system. The method includes providing the virtual memory address at a source node, determining that the virtual memory address is to be sent to a remote node, sending the virtual memory address to the remote node, and translating the virtual memory address on the remote node into a physical memory address using a remote-translation table (RTT). The RTT co...

대표
청구항

1. A method for remotely translating a virtual memory address into a physical memory address in a multi-node system, the method comprising:providing the virtual memory address at a source node; determining that the virtual memory address is to be sent to a remote node; sending the virtual memory address to the remote node; and translating the virtual memory address on the remote node into a physical memory addressing using a remote-translation table (RTT), wherein the RTT contains translation information for an entire virtual memory address space associa...

이 특허를 인용한 특허 피인용횟수: 26

  1. Faanes,Gregory J.; Scott,Steven L.; Lundberg,Eric P.; Moore, Jr.,William T.; Johnson,Timothy J.. Decoupled scalar/vector computer architecture system and method. USP2008027334110.
  2. Scott, Steven L.; Faanes, Gregory J.. Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system. USP2010067743223.
  3. Carpentier, Paul R. M.; Turpin, Russell. Elimination of duplicate objects in storage clusters. USP2014098843454.
  4. Baker, Don; Carpentier, Paul R. M.; Klager, Andrew; Pierce, Aaron; Ring, Jonathan; Turpin, Russell; Yoakley, David. Erasure coding and replication in storage clusters. USP2018039916198.
  5. Baker, Don; Carpentier, Paul R. M.; Klager, Andrew; Pierce, Aaron; Ring, Jonathan; Turpin, Russell; Yoakley, David. Erasure coding and replication in storage clusters. USP2015099148174.
  6. Gordon, Mark R.. I/O mapping-path tracking in a storage configuration. USP2013028380894.
  7. Kohn,James R.. Indirectly addressed vector load-operate-store method and apparatus. USP2008047366873.
  8. Scott, Steven L.. Latency tolerant distributed shared memory multiprocessor computer. USP2009067543133.
  9. Pautsch, Gregory W.; Pautsch, Adam. Method and apparatus for cooling electronic components. USP2010077757497.
  10. Kohn, James R.. Method and apparatus for indirectly addressed vector load-add-store across multi-processors. USP2010097793073.
  11. Kohn,James R.. Method and apparatus for indirectly addressed vector load-add-store across multi-processors. USP2008097421565.
  12. Savagaonkar, Uday; Sahita, Ravi; Durham, David. Monitoring a target agent execution pattern on a VT-enabled system. USP2010097802050.
  13. Scott,Steven L.; Faanes,Gregory J.; Stephenson,Brick; Moore, Jr.,William T.; Kohn,James R.. Multistream processing memory-and barrier-synchronization method and apparatus. USP2008107437521.
  14. Krakirian, Shahe Hagop; Akkawi, Isam. Node identification for distributed shared memory system. USP201311RE44610.
  15. Scott, Steven L.; Faanes, Gregory J.; Stephenson, Brick; Moore, Jr., William T.; Kohn, James R.. Relaxed memory consistency model. USP2012118307194.
  16. Sheets, Kitrick; Hastings, Andrew B.. Remote translation mechanism for a multinode system. USP2009087577816.
  17. Klausler, Peter M.. Scheduling synchronization of programs running as streams on multiple processors. USP2010067735088.
  18. Sheets,Kitrick; Williams,Josh; Gettler,Jonathan; Piatz,Steve; Hastings,Andrew B.; Hill,Peter; Bravatto,James G.; Kohn,James R.; Titus,Greg. Scheduling synchronization of programs running as streams on multiple processors. USP2009037503048.
  19. Sheets, Kitrick. Sharing memory within an application using scalable hardware resources. USP2009057529906.
  20. Leinberger, William J.; Kowalski, Bobby Jim; Denny, Ronald R.. System and method for managing addresses in a computing system. USP2011108037259.
  21. Faanes, Gregory J.; Lundberg, Eric P.; Scott, Steven L.; Baird, Robert J.. System and method for processing memory instructions using a forced order queue. USP2009047519771.
  22. Savagaonkar, Uday; Sahita, Ravi; Durham, David; Khosravi, Hormuzd. Tamper protection of software agents operating in a vitual technology environment methods and apparatuses. USP2011027882318.
  23. Carpentier, Paul R. M.; Turpin, Russell. Two level addressing in storage clusters. USP2018049952918.
  24. Carpentier, Paul R. M.; Turpin, Russell. Two level addressing in storage clusters. USP2015089104560.
  25. Carpentier, Paul R. M.; Turpin, Russell. Two level addressing in storage clusters. USP2017029575826.
  26. Carpentier, Paul R.M.; Turpin, Russell. Two level addressing in storage clusters. USP2015099128833.