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A system and method for coupling read data signals and write data signals through I/O lines of a memory array. Precharge circuits precharge alternating signal lines to high and low precharge voltages. An accelerate high circuit coupled to each of the I/O lines that has been precharged low detects an

A system and method for coupling read data signals and write data signals through I/O lines of a memory array. Precharge circuits precharge alternating signal lines to high and low precharge voltages. An accelerate high circuit coupled to each of the I/O lines that has been precharged low detects an increase in the voltage of the I/O line above the precharge low voltage. The accelerate high circuit then drives the I/O line toward a high voltage, such as VCC. Similarly, an accelerate low circuit coupled to each of the I/O lines that has been precharged high detects a decrease in the voltage of the I/O line below the precharge high voltage. The accelerate low circuit then drives the I/O line to a low voltage, such as ground.

대표청구항 ▼

1. A signal accelerator system for accelerating the coupling of a digital signal through a signal line, the system comprising:a precharge low circuit coupled to the signal line, the precharge low circuit being operable to precharge the signal line to a precharge low voltage when the precharge low ci

1. A signal accelerator system for accelerating the coupling of a digital signal through a signal line, the system comprising:a precharge low circuit coupled to the signal line, the precharge low circuit being operable to precharge the signal line to a precharge low voltage when the precharge low circuit is enabled; and an accelerate high circuit coupled to the signal line, the accelerate high circuit being operable to drive the signal line toward a predetermined high voltage responsive to detecting that the voltage of the signal line is greater than a predetermined low voltage. 2. The signal accelerator system of claim 1 wherein the predetermined low voltage is substantially equal to the precharge low voltage.3. The signal accelerator system of claim 1 wherein the predetermined high voltage is substantially equal to VCC?VTT, and the predetermined low voltage is substantially equal to VT, where VCC is a power supply voltage and VT is a transistor threshold voltage.4. The signal accelerator system of claim 3 wherein the precharge low voltage is substantially equal to VT.5. The signal accelerator system of claim 3 wherein the accelerate high circuit is operable to drive the signal line toward VCC.6. The signal accelerator system of claim 5 wherein the accelerate high circuit is operable to terminate driving the signal line toward VCC responsive to the signal line reaching a voltage of VCC?VT.7. The signal accelerator system of claim 1 wherein the precharge low circuit comprises:a drive circuit that drives the signal line toward the precharge low voltage when the precharge low circuit is enabled, the drive circuit driving the signal line toward the precharge low voltage until a drive terminate signal is generated; and a sense circuit that senses when the voltage on the signal line reaches the precharge low voltage, the sense circuit being operable to generate the drive terminate signal when the sense circuit senses that the voltage on the signal line has reached the precharge low voltage. 8. The signal accelerator system of claim 7 wherein the precharge low circuit further comprises an isolation circuit the effectively isolates the precharge low circuit from the signal line when the precharge circuit is not enabled.9. The signal accelerator system of claim 1 wherein the accelerate high circuit comprises:a sense circuit that is operable to sense when the voltage on the signal line is greater than the predetermined low voltage, the sense circuit being operable to generate a drive signal responsive to sensing that the voltage on the signal line is greater than the predetermined low voltage; and a drive circuit that is responsive to the drive signal to drive the signal line toward the precharge high voltage. 10. The signal accelerator system of claim 9 wherein the accelerate high circuit further comprises an isolation circuit the effectively isolates the accelerate high circuit from the signal line when the accelerate high circuit is not enabled.11. A signal accelerator system for accelerating the coupling of a digital signal through a signal line, the system comprising:a precharge high circuit coupled to the signal line, the precharge high circuit being operable to precharge the signal line to which it is coupled to a precharge high voltage when the precharge high circuit is enabled; and an accelerate low circuit coupled to the signal line, the accelerate low circuit being operable to drive the signal line to which it is coupled toward a predetermined low voltage responsive to detecting that the voltage of the signal line is less than a predetermined high voltage. 12. The signal accelerator system of claim 11 wherein the predetermined high voltage is substantially equal to the precharge high voltage.13. The signal accelerator system of claim 11 wherein the predetermined high voltage is substantially equal to VCC?VT, and the predetermined low voltage is substantially equal to VT, where VCC is a power supply voltage and VT is a transistor threshold voltage.14. The signal accelerator system of claim 13 wherein the precharge high voltage is substantially equal to VCC?VT.15. The signal accelerator system of claim 13 wherein the accelerate low circuit is operable to drive the signal line toward zero volts.16. The signal accelerator system of claim 15 wherein the accelerate low circuit is operable to terminate driving the signal line to which it is coupled toward zero volts responsive to the signal line reaching a voltage of VT.17. The signal accelerator system of claim 11 wherein the precharge high circuit comprises:a drive circuit that drives the signal line toward the precharge high voltage when the precharge high circuit is enabled, the drive circuit driving the signal line toward the precharge high voltage until a drive terminate signal is generated; and a sense circuit that senses when the voltage on the signal line reaches the precharge high voltage, the sense circuit being operable to generate the drive terminate signal when the sense circuit senses that the voltage on the signal line has reached the precharge high voltage. 18. The signal accelerator system of claim 17 wherein the precharge high circuit further comprises an isolation circuit the effectively isolates the precharge high circuit from the signal line when the precharge high circuit is not enabled.19. The signal accelerator system of claim 11 wherein the accelerate low circuit comprises:a sense circuit that is operable to sense when the voltage on the signal line is less than the predetermined high voltage, the sense circuit being operable to generate a drive signal responsive to sensing that the voltage on the signal line is less than the predetermined high voltage; and a drive circuit that is responsive to the drive signal to drive the signal line toward the precharge low voltage. 20. The signal accelerator system of claim 19 wherein the accelerate low circuit further comprises an isolation circuit the effectively isolates the accelerate circuit from the signal line when the accelerate low circuit is not enabled.21. A signal accelerator system for accelerating the coupling of digital signals through respective signal lines, the system comprising:a plurality of first circuits coupled to respective alternating ones of the signal lines, each of the first circuits being operable to precharge the signal line to which it is coupled to a precharge low voltage and to drive the signal line to which it is coupled toward a first predetermined high voltage responsive to detecting that the voltage of the signal line is greater than a first predetermined low voltage; and a plurality of second circuits coupled to respective ones of each of the signal lines to which a first circuit is not coupled, each of the second circuits being operable to precharge the signal line to which it is coupled to a precharge high voltage and to drive the signal line to which it is coupled toward a second predetermined low voltage responsive to detecting that the voltage of the signal line is less than a second predetermined high voltage. 22. The signal accelerator system of claim 21 wherein the first and second predetermined high voltages are substantially equal to the precharge high voltage, and the first and second predetermined low voltages are substantially equal to the precharge low voltage.23. The signal accelerator system of claim 21 wherein the precharge high voltage is substantially equal to VCC?VT, and the precharge low voltage is substantially equal to VT, where VCC is a power supply voltage and VT is a transistor threshold voltage.24. The signal accelerator system of claim 23 wherein the first predetermined high voltage comprises VCC, and the second predetermined low voltage comprises zero volts.25. The signal accelerator system of claim 23 wherein the first predetermined low voltage comprises VT, and wherein the second predetermined high voltage comprises VCC?VT.26. The signal accelerator system of claim 21 wherein each of the first circuits is operable to terminate driving the signal line to which it is coupled toward the first predetermined high voltage responsive to the signal line reaching the first predetermined high voltage less a voltage of VT, and each of the second circuits is operable to terminate driving the signal line to which it is coupled toward the second predetermined low voltage responsive to the signal line reaching a voltage of VT, where VT is a transistor threshold voltage.27. A memory device, comprising:a command decoder receiving memory command signals through externally accessible command input terminals, the command decoder generating memory control signals responsive to predetermined combinations of the command signals; an address decoder receiving address signals through externally accessible address input terminals, the address decoder generating row and column addressing signals responsive to the address signals; a memory bank, comprising: a plurality of memory arrays, each of the memory arrays comprising a plurality of memory cells arranged in rows and columns, and a sense amplifier for each column of memory cells; a respective I/O line extending from each of the memory arrays, the I/O lines extending through the memory bank adjacent to each other; a respective precharge low circuit coupled at least some of the I/O lines, each of the precharge low circuits being operable to precharge the I/O line to which it is coupled to a precharge low voltage when the precharge low circuit is enabled; and a respective accelerate high circuit coupled to each of the I/O lines to which one of the precharge low circuits is coupled, the accelerate high circuit being operable to drive the I/O line to which it is coupled toward a predetermined high voltage responsive to detecting that the voltage of the I/O line is greater than a predetermined low voltage; and a data path extending between a plurality of externally accessible data bus terminals and the I/O lines for coupling data signals to and from the memory arrays. 28. The memory device of claim 27 wherein the predetermined low voltage is substantially equal to the precharge low voltage.29. The memory device of claim 27 wherein the predetermined high voltage is substantially equal to VCC?VT, and the predetermined low voltage is substantially equal to VT, where VCC is a power supply voltage and VT is a transistor threshold voltage.30. The memory device of claim 29 wherein the precharge low voltage is substantially equal to VT.31. The memory device of claim 29 wherein the accelerate high circuit is operable to drive the signal line toward VCC.32. The memory device of claim 31 wherein the accelerate high circuit is operable to terminate driving the signal line toward VCC responsive to the signal line reaching a voltage of VCC?VT.33. The memory device of claim 27 wherein the precharge low circuit comprises:a drive circuit that drives the signal line toward the precharge low voltage when the precharge low circuit is enabled, the drive circuit driving the signal line toward the precharge low voltage until a drive terminate signal is generated; and a sense circuit that senses when the voltage on the signal line reaches the precharge low voltage, the sense circuit being operable to generate the drive terminate signal when the sense circuit senses that the voltage on the signal line has reached the precharge low voltage. 34. The memory device of claim 33 wherein the precharge low circuit further comprises an isolation circuit the effectively isolates the precharge low circuit from the signal line when the precharge circuit is not enabled.35. The memory device of claim 27 wherein the accelerate high circuit comprises:a sense circuit that is operable to sense when the voltage on the signal line is greater than the predetermined low voltage, the sense circuit being operable to generate a drive signal responsive to sensing that the voltage on the signal line is greater than the predetermined low voltage; and a drive circuit that is responsive to the drive signal to drive the signal line toward the precharge high voltage. 36. The memory device of claim 35 wherein the accelerate high circuit further comprises an isolation circuit the effectively isolates the accelerate high circuit from the signal line when the accelerate high circuit is not enabled.37. The memory device of claim 27 wherein the memory cells in each of the memory arrays comprise dynamic random access memory cells.38. A memory device, comprising:a command decoder receiving memory command signals through externally accessible command input terminals, the command decoder generating memory control signals responsive to predetermined combinations of the command signals; an address decoder receiving address signals through externally accessible address input terminals, the address decoder generating row and column addressing signals responsive to the address signals; a memory bank, comprising: a plurality of memory arrays, each of the memory arrays comprising a plurality of memory cells arranged in rows and columns, and a sense amplifier for each column of memory cells; a respective I/O line extending from each of the memory arrays, the I/O lines extending through the memory bank adjacent to each other; a respective precharge high circuit coupled to at least some of the I/O lines, each of the precharge high circuits being operable to precharge the I/O line to which it is coupled to a precharge high voltage when the precharge high circuit is enabled; and a respective accelerate low circuit coupled to each of the I/O lines to which one of the precharge high circuits is coupled, the accelerate low circuit being operable to drive the I/O line to which it is coupled toward a predetermined low voltage responsive to detecting that the voltage of the I/O line is less than a predetermined high voltage; and a data path extending between a plurality of externally accessible data bus terminals and the I/O lines for coupling data signals to and from the memory arrays. 39. The memory device of claim 38 wherein the predetermined high voltage is substantially equal to the precharge high voltage.40. The memory device of claim 38 wherein the predetermined high voltage is substantially equal to VCC?VT, and the predetermined low voltage is substantially equal to VT, where VCC is a power supply voltage and VT is a transistor threshold voltage.41. The memory device of claim 40 wherein the precharge high voltage is substantially equal to VCC?VT.42. The memory device of claim 40 wherein the accelerate low circuit is operable to drive the signal line toward zero volts.43. The memory device of claim 42 wherein the accelerate low circuit is operable to terminate driving the signal line to which it is coupled toward zero volts responsive to the signal line reaching a voltage of VT.44. The memory device of claim 38 wherein the precharge high circuit comprises:a drive circuit that drives the signal line toward the precharge high voltage when the precharge high circuit is enabled, the drive circuit driving the signal line toward the precharge high voltage until a drive terminate signal is generated; and a sense circuit that senses when the voltage on the signal line reaches the precharge high voltage, the sense circuit being operable to generate the drive terminate signal when the sense circuit senses that the voltage on the signal line has reached the precharge high voltage. 45. The memory device of claim 44 wherein the precharge high circuit further comprises an isolation circuit the effectively isolates the precharge high circuit from the signal line when the precharge high circuit is not enabled.46. The memory device of claim 38 wherein the accelerate low circuit comprises:a sense circuit that is operable to sense when the voltage on the signal line is less than the predetermined high voltage, the sense circuit being operable to generate a drive signal responsive to sensing that the voltage on the signal line is less than the predetermined high voltage; and a drive circuit that is responsive to the drive signal to drive the signal line toward the precharge low voltage. 47. The memory device of claim 46 wherein the accelerate low circuit further comprises an isolation circuit the effectively isolates the accelerate circuit from the signal line when the accelerate low circuit is not enabled.48. The memory device of claim 38 wherein the memory cells in each of the memory arrays comprise dynamic random access memory cells.49. A memory device, comprising:a command decoder receiving memory command signals through externally accessible command input terminals, the command decoder generating memory control signals responsive to predetermined combinations of the command signals; an address decoder receiving address signals through externally accessible address input terminals, the address decoder generating row and column addressing signals responsive to the address signals; a memory bank, comprising: a plurality of memory arrays, each of the memory arrays comprising a plurality of memory cells arranged in rows and columns, and a sense amplifier for each column of memory cells; a respective I/O line extending from each of the memory arrays, the I/O lines extending through the memory bank adjacent to each other; a plurality of first circuits coupled to respective alternating ones of the I/O lines, each of the first circuits being operable to precharge the I/O line to which it is coupled to a precharge low voltage and to drive the I/O line to which it is coupled toward a first predetermined high voltage responsive to detecting that the voltage of the I/O line is greater than a first predetermined low voltage; and a plurality of second circuits coupled to respective ones of each of the I/O lines to which a first circuit is not coupled, each of the second circuits being operable to precharge the I/O line to which it is coupled to a precharge high voltage and to drive the I/O line to which it is coupled toward a second predetermined low voltage responsive to detecting that the voltage of the signal line is less than a second predetermined high voltage; and a data path extending between a plurality of externally accessible data bus terminals and the I/O lines for coupling data signals to and from the memory arrays. 50. The memory device of claim 49 wherein the first and second predetermined high voltages are substantially equal to the precharge high voltage, and the first and second predetermined low voltages are substantially equal to the precharge low voltage.51. The memory device of claim 49 wherein the precharge high voltage is substantially equal to VCC?VT, and the precharge low voltage is substantially equal to VT, where VCC is a power supply voltage and VT is a transistor threshold voltage.52. The memory device of claim 51 wherein the first predetermined high voltage comprises VCC, and the second predetermined low voltage comprises zero volts.53. The memory device of claim 51 wherein the first predetermined low voltage comprises VT, and wherein the second predetermined high voltage comprises VCC?VT.54. The memory device of claim 49 wherein each of the first circuits is operable to terminate driving the signal line to which it is coupled toward the first predetermined high voltage responsive to the signal line reaching the first predetermined high voltage less a voltage of VT, and each of the second circuits is operable to terminate driving the signal line to which it is coupled toward the second predetermined low voltage responsive to the signal line reaching a voltage of VT, where VT is a transistor threshold voltage.55. The memory device of claim 49 wherein the memory cells in each of the memory arrays comprise dynamic random access memory cells.56. A computer system, comprising:an integrated circuit processor having a plurality of externally accessible terminals coupled to a processor bus; an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and a dynamic random access memory coupled to a processor bus, the dynamic random access memory comprising: a command decoder receiving memory command signals through externally accessible command input terminals, the command decoder generating memory control signals responsive to predetermined combinations of the command signals; an address decoder receiving address signals through externally accessible address input terminals, the address decoder generating row and column addressing signals responsive to the address signals; a memory bank comprising: a plurality of memory arrays, each of the memory arrays comprising a plurality of memory cells arranged in rows and columns, and a sense amplifier for each column of memory cells; a respective I/O line extending from each of the memory arrays, the I/O lines extending through the memory bank adjacent to each other; a respective precharge low circuit coupled at least some of the I/O lines, each of the precharge low circuits being operable to precharge the I/O line to which it is coupled to a precharge low voltage when the precharge low circuit is enabled; and a respective accelerate high circuit coupled to each of the I/O lines to which one of the precharge low circuits is coupled, the accelerate high circuit being operable to drive the I/O line to which it is coupled toward a predetermined high voltage responsive to detecting that the voltage of the I/O line is greater than a predetermined low voltage; and a data path extending between a plurality of externally accessible data bus terminals and the I/O lines for coupling data signals to and from the memory array. 57. The computer system of claim 56 wherein the predetermined low voltage is substantially equal to the precharge low voltage.58. The computer system of claim 56 wherein the predetermined high voltage is substantially equal to VCC?VT, and the predetermined low voltage is substantially equal to VT, where VCC is a power supply voltage and VT is a transistor threshold voltage.59. The computer system of claim 58 wherein the precharge low voltage is substantially equal to VT.60. The computer system of claim 58 wherein the accelerate high circuit is operable to drive the signal line toward VCC.61. The computer system of claim 60 wherein the accelerate high circuit is operable to terminate driving the signal line toward VCC responsive to the signal line reaching a voltage of VCC?VT.62. The computer system of claim 56 wherein the precharge low circuit comprises:a drive circuit that drives the signal line toward the precharge low voltage when the precharge low circuit is enabled, the drive circuit driving the signal line toward the precharge low voltage until a drive terminate signal is generated; and a sense circuit that senses when the voltage on the signal line reaches the precharge low voltage, the sense circuit being operable to generate the drive terminate signal when the sense circuit senses that the voltage on the signal line has reached the precharge low voltage. 63. The computer system of claim 62 wherein the precharge low circuit further comprises an isolation circuit the effectively isolates the precharge low circuit from the signal line when the precharge circuit is not enabled.64. The computer system of claim 56 wherein the accelerate high circuit comprises:a sense circuit that is operable to sense when the voltage on the signal line is greater than the predetermined low voltage, the sense circuit being operable to generate a drive signal responsive to sensing that the voltage on the signal line is greater than the predetermined low voltage; and a drive circuit that is responsive to the drive signal to drive the signal line toward the precharge high voltage. 65. The computer system of claim 64 wherein the accelerate high circuit further comprises an isolation circuit the effectively isolates the accelerate high circuit from the signal line when the accelerate high circuit is not enabled.66. A computer system, comprising:an integrated circuit processor having a plurality of externally accessible terminals coupled to a processor bus; an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and a dynamic random access memory coupled to a processor bus, the dynamic random access memory comprising: a command decoder receiving memory command signals through externally accessible command input terminals, the command decoder generating memory control signals responsive to predetermined combinations of the command signals; an address decoder receiving address signals through externally accessible address input terminals, the address decoder generating row and column addressing signals responsive to the address signals; a memory bank comprising: a plurality of memory arrays, each of the memory arrays comprising a plurality of memory cells arranged in rows and columns, and a sense amplifier for each column of memory cells; a respective I/O line extending from each of the memory arrays, the I/O lines extending through the memory bank adjacent to each other; a respective precharge high circuit coupled to at least some of the I/O lines, each of the precharge high circuits being operable to precharge the I/O line to which it is coupled to a precharge high voltage when the precharge high circuit is enabled; and a respective accelerate low circuit coupled to each of the I/O lines to which one of the precharge high circuits is coupled, the accelerate low circuit being operable to drive the I/O line to which it is coupled toward a predetermined low voltage responsive to detecting that the voltage of the I/O line is less than a predetermined high voltage; and a data path extending between a plurality of externally accessible data bus terminals and the I/O lines for coupling data signals to and from the memory array. 67. The computer system of claim 66 wherein the predetermined high voltage is substantially equal to the precharge high voltage.68. The computer system of claim 66 wherein the predetermined high voltage is substantially equal to VCC?VT, and the predetermined low voltage is substantially equal to VT, where VCC is a power supply voltage and VT is a transistor threshold voltage.69. The computer system of claim 68 wherein the precharge high voltage is substantially equal to VCC?VT.70. The computer system of claim 68 wherein the accelerate low circuit is operable to drive the signal line toward zero volts.71. The computer system of claim 70 wherein the accelerate low circuit is operable to terminate driving the signal line to which it is coupled toward zero volts responsive to the signal line reaching a voltage of VT.72. The computer system of claim 66 wherein the precharge high circuit comprises:a drive circuit that drives the signal line toward the precharge high voltage when the precharge high circuit is enabled, the drive circuit driving the signal line toward the precharge high voltage until a drive terminate signal is generated; and a sense circuit that senses when the voltage on the signal line reaches the precharge high voltage, the sense circuit being operable to generate the drive terminate signal when the sense circuit senses that the voltage on the signal line has reached the precharge high voltage. 73. The computer system of claim 72 wherein the precharge high circuit further comprises an isolation circuit the effectively isolates the precharge high circuit from the signal line when the precharge high circuit is not enabled.74. The computer system of claim 66 wherein the accelerate low circuit comprises:a sense circuit that is operable to sense when the voltage on the signal line is less than the predetermined high voltage, the sense circuit being operable to generate a drive signal responsive to sensing that the voltage on the signal line is less than the predetermined high voltage; and a drive circuit that is responsive to the drive signal to drive the signal line toward the precharge low voltage. 75. The computer system of claim 74 wherein the accelerate low circuit further comprises an isolation circuit the effectively isolates the accelerate circuit from the signal line when the accelerate low circuit is not enabled.76. A computer system, comprising:an integrated circuit processor having a plurality of externally accessible terminals coupled to a processor bus; an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and a dynamic random access memory coupled to a processor bus, the dynamic random access memory comprising: a command decoder receiving memory command signals through externally accessible command input terminals, the command decoder generating memory control signals responsive to predetermined combinations of the command signals; an address decoder receiving address signals through externally accessible address input terminals, the address decoder generating row and column addressing signals responsive to the address signals; a memory bank comprising: a plurality of memory arrays, each of the memory arrays comprising a plurality of memory cells arranged in rows and columns, and a sense amplifier for each column of memory cells; a respective I/O line extending from each of the memory arrays, the I/O lines extending through the memory bank adjacent to each other; a plurality of first circuits coupled to respective alternating ones of the I/O lines, each of the first circuits being operable to precharge the I/O line to which it is coupled to a precharge low voltage and to drive the I/O line to which it is coupled toward a first predetermined high voltage responsive to detecting that the voltage of the I/O line is greater than a first predetermined low voltage; and a plurality of second circuits coupled to respective ones of each of the I/O lines to which a first circuit is not coupled, each of the second circuits being operable to precharge the I/O line to which it is coupled to a precharge high voltage and to drive the I/O line to which it is coupled toward a second predetermined low voltage responsive to detecting that the voltage of the signal line is less than a second predetermined high voltage; and a data path extending between a plurality of externally accessible data bus terminals and the I/O lines for coupling data signals to and from the memory array. 77. The computer system of claim 76 wherein the first and second predetermined high voltages are substantially equal to the precharge high voltage, and the first and second predetermined low voltages are substantially equal to the precharge low voltage.78. The computer system of claim 76 wherein the precharge high voltage is substantially equal to VCC?VT, and the precharge low voltage is substantially equal to VT, where VCC is a power supply voltage and VT is a transistor threshold voltage.79. The computer system of claim 78 wherein the first predetermined high voltage comprises VCC, and the second predetermined low voltage comprises zero volts.80. The computer system of claim 78 wherein the first predetermined low voltage comprises VT, and wherein the second predetermined high voltage comprises VCC?VT.81. The computer system of claim 76 wherein each of the first circuits is operable to terminate driving the signal line to which it is coupled toward the first predetermined high voltage responsive to the signal line reaching the first predetermined high voltage less a voltage of VT, and each of the second circuits is operable to terminate driving the signal line to which it is coupled toward the second predetermined low voltage responsive to the signal line reaching a voltage of VT, where VT is a transistor threshold voltage.82. The computer system of claim 76 wherein the memory cells in each of the memory arrays comprise dynamic random access memory cells.83. A method of coupling a plurality of digital signals through a respective plurality of signal lines extending in parallel to each other, the method comprising:precharging a first alternating set of the signal lines to a first voltage; precharging a second set of the signal lines alternating with the signal lines in the first set to a second voltage, the second voltage having a larger magnitude than the first voltage; after precharging the signal lines in the first set to the first voltage, detecting whether the voltage of any of the signal in the first set has increased from the first voltage; after precharging the signal lines in the second set to the second voltage, detecting whether the voltage of any of the signal lines in the second set has decreased from the second voltage; in response to detecting that the voltage of any of the signal lines in the first set has increased above the first voltage, driving the signal line toward a third voltage that is larger than the first voltage; and in response to detecting that the voltage of any of the signal lines in the second set has decreased below the second voltage, driving the signal line toward a fourth voltage that is larger than the second voltage. 84. The method of claim 83 wherein the signal lines comprise input/output lines coupled to an array of memory cells.85. The method of claim 83 wherein the first voltage comprises VT, where VT is a threshold voltage of a transistor in the memory array, and wherein the second voltage comprises VCC?VT, where VCC is a voltage supplying power to the memory array.86. The method of claim 85 wherein the third voltage comprises VCC and the fourth voltage comprises zero volts.87. The method of claim 83, further comprising:terminating the act of driving the I/O line in the first set toward the third voltage when the voltage of the I/O line has increased to the second voltage; and terminating the act of driving the I/O line in the second set toward the fourth voltage when the voltage of the I/O line has decreased to the first voltage. 88. The method of claim 87 wherein the first voltage comprises VT, where VT is the threshold voltage of a transistor in the memory array, the second voltage comprises VCC?VT, where VCC is a voltage supplying power to the memory array, the third voltage comprises VCC, and the fourth voltage comprises zero volts.