[특허]Narrow reactive edge treatments and method for fabrication

E-Tenna Corporation

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특허 상세정보

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내보내기 페이스북 공유 트위터 공유 카카오톡 공유

Narrow reactive edge treatments and method for fabrication

특허상세정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01Q-001/24
미국특허분류(USC)	343/702; 343/909; 343/700.MS
출원번호	US-0367179 (2003-02-14)
발명자 / 주소	Mendolia, Greg S. Rogers, Shawn McKinzie, III, William E.
출원인 / 주소	E-Tenna Corporation
대리인 / 주소	Brinks Hofer Gilson &
인용정보	피인용 횟수 : 23 인용 특허 : 4

초록
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An electromagnetic bandgap material is electrically attached to an edge, and enables high isolation between antennas due to the attenuation of surface waves. The disclosed embodiments further provide narrow reactive edge treatments in the form of artificial magnetic conductors (AMCs) whose physical width is less than 1/10 of a free space wavelength for the frequency of surface currents intended to be suppressed. These embodiments still further provide several AMCs suitable for this purpose, along with several exemplary manufacturing techniques for the AM...

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1. A reactive circuit configured to inhibit the flow of electric currents along an edge of a conducting surface, the reactive circuit being characterizable as a ladder network of series capacitors at an outermost portion of the edge and shunt inductors that connect at least a subset of the series capacitors to the conducting surface, the ladder network having a periodic structure with period P which is much less than a free space wavelength λ for frequencies at which edge currents are inhibited.2. The reactive circuit of claim 1 further comprising:an array of patches defining at least in part the series capacitors; and an array of orthogonal conductors electrically positioned between patches of the array of patches and the conducting surface and defining at least in part the shunt inductors. 3. The reactive circuit of claim 2 further comprising:a second array of patches, each patch of the second array of patches overlapping adjacent patches of the array of patches to define at least in part the series capacitors. 4. The reactive circuit of claim 2 further comprising:spiral inductors electrically positioned between patches of the array of patches and the conducting surface to define at least in part the shunt inductors. 5. A reactive edge treatment configured to be disposed on an electrically conductive edge, the reactive edge treatment comprising:a substrate, the substrate having a width which is 1/10 of a free space wavelength at frequencies where the reactive edge treatment inhibits flow of edge currents in the electrically conductive edge, the substrate including a conductive backplane, one or more substantially planar arrays of conductive patches spaced from the conductive backplane, and an array of orthogonal conductors, each orthogonal conductor extending from a patch to connect the conductive backplane to at least one patch. 6. The reactive edge treatment of claim 5 wherein the one or more arrays of conductive patches comprises:a first array of patches, each patch of the first array being electrically coupled to an orthogonal conductor. 7. The reactive edge treatment of claim 6 wherein the one or more arrays of conductive patches further comprises:a second array of patches, each patch of the second array overlapping adjacent patches of the first array. 8. The reactive edge treatment of claim 6 further comprising capacitors enhance series capacitance between adjacent patches of the first array of patches.9. The reactive edge treatment of claim 6 further comprising chip capacitors between adjacent patches of the first array of patches.10. The reactive edge treatment of claim 6 further comprising interdigitated capacitors between at least some adjacent patches of the first array of patches.11. The reactive edge treatment of claim 5 wherein at least some orthogonal conductors include inductance enhancements between the patch and the conductive backplane.12. The reactive edge treatment of claim 5 further comprising:spiral inductors associated with at least some of the orthogonal conductors and positioned between the patch and the conductive backplane. 13. A reactive edge treatment configured to be disposed on an electrically conductive edge, the reactive edge treatment comprising:a flexible substrate; a first central plate and a first array of patches disposed on an obverse side of the flexible substrate, patches of the first array of patches being electrically coupled to the first central plate; and a second array of patches disposed on a reverse side of the flexible substrate, patches of the second array of patches being positioned to overlap adjacent patches of the first array. 14. The reactive edge treatment of claim 13 further comprising spirals extending from the patches of the second array of patches.15. A reactive edge treatment configured to be disposed on an electrically conductive edge, the reactive edge treatment comprising:a printed circuit including a conductive radio frequency (RF) backplane, one or more substantially planar arrays of conductive patches located at fixed distances from the RF backplane, and an array of plated through holes, each hole being generally centered on a patch of at least one of the planar arrays of conductive patches, the plated through holes connecting the RF backplane to the at least one array of patches, the reactive edge treatment having a width which is less than 1/10 of a free space wavelength at frequencies where the reactive edge treatment inhibits flow of edge currents in the electrically conductive edge. 16. The reactive edge treatment of claim 15 further comprising a dielectric layer spacing the backplane and the one or more planar arrays.17. The reactive edge treatment of claim 15 wherein the one or more arrays of conductive patches comprises:a first may of patches, each patch of the first array being electrically coupled to a plated through hole; and a second array of patches, each patch of the second array overlapping adjacent patches of the first array. 18. The reactive edge treatment of claim 17 further comprising capacitors to enhance series capacitance between adjacent patches of the first array of patches.19. The reactive edge treatment of claim 17 further comprising inductors to enhance shunt inductance between at least some patches of the first array of patches and the backplane.20. A method for manufacturing a reactive edge treatment, the method comprising:forming a planar metal lead frame having a center strip and a row of patches, connected to the center strip through tabs on one or both sides of the center strip; and folding each row of patches into a secondary plane, the secondary plane being substantially parallel to the center strip, through two successive bends of the connecting tabs. 21. The method of claim 20 further comprising: connecting the center strip to a conductive edge.22. The method of claim 20 further comprising the integration of loop inductors or meanderline inductors into the tabs.23. A reactive edge treatment configured to be disposed on an electrically conductive edge, the reactive edge treatment comprising:a flexible substrate; on a first side of the substrate, a central plate and an array of conductive patches, each conductive patch separated from the central plate by an inductive trace; and on a second side of the substrate, a plurality of conductive patches positioned to at least partially overlap patches of the array of conductive patches, the substrate being flexible to orient the central plate in a first plane and the array of conductive patches in a second plane, the second plane having a predetermined orientation relative to the first plane. 24. The reactive edge treatment of claim 23 wherein the second plane is substantially parallel to the first plane.25. A reactive edge treatment configured to be disposed on an electrically conductive edge, the reactive edge treatment comprising:one or more substantially planar arrays of conductive patches, each patch including an annular ring portion and a spiral inductor portion, the spiral inductor portion electrically positioned between the annular ring portion and a patch contact, and an array of conductive vias, each conductive via extending from a patch contact of a patch to electrically connect the patch to the electrically conductive edge. 26. The reactive edge treatment of claim 25 wherein the annular ring portion and the spiral inductor portion are substantially coplanar.

이 특허에 인용된 특허 (4)

이 특허를 인용한 특허 피인용횟수: 23

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특허 상세정보

Narrow reactive edge treatments and method for fabrication

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이 특허에 인용된 특허 (4)

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Narrow reactive edge treatments and method for fabrication

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이 특허에 인용된 특허 (4)

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