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A novel technique for the enhancement of yield and speed of semiconductor integrated circuits using post fabrication transistor mismatch compensation circuitry is provided. The system has a sense amplifier, a multiplexer, delay elements, and a provision for hardwiring fast and slow circuits during p

A novel technique for the enhancement of yield and speed of semiconductor integrated circuits using post fabrication transistor mismatch compensation circuitry is provided. The system has a sense amplifier, a multiplexer, delay elements, and a provision for hardwiring fast and slow circuits during packaging of a memory circuit. The sense amplifier firing path is split into a slow and a fast path and the multiplexer can select either the slow path or fast path. The memory circuit is tested after fabrication to assess whether each memory cell can be identified as slow or fast circuits and accordingly the fast path or slow path is selected by the multiplexer. The path for each memory cell may be then hardwired during packaging by connecting a select input of multiplexer to a VDD signal or a ground signal.

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1. A system for high yield and speed enhancement of semiconductor integrated circuits such as SRAM and DRAM using post fabrication transistor mismatch compensation circuitry comprising: a sense amplifier for providing high memory yield and speed enhancement using post fabrication, transistor mismatc

1. A system for high yield and speed enhancement of semiconductor integrated circuits such as SRAM and DRAM using post fabrication transistor mismatch compensation circuitry comprising: a sense amplifier for providing high memory yield and speed enhancement using post fabrication, transistor mismatch compensation circuit, wherein a sense amplifier firing path is split into two paths, one path corresponding to fast chips and the other to the slow chips, and a multiplexer which selects one of the two paths to fire the sense amplifier such that more than 80 % of the memory integrated circuits work as fast circuits (fast path) and a remainder of the memory integrated circuits are still functional (slow path) without compromising the yield; anddelay elements for effecting delay in the fast and slow paths. 2. A system for high yield and speed enhancement of semiconductor integrated circuits as claimed in claim 1, wherein the delay in the sense amplifier fast and slow firing paths are adjusted depending on the required design index.3. A system for high yield and speed enhancement of semiconductor integrated circuits as claimed in claim 1, wherein the fast path corresponds to a first design index and the slow path corresponds to a second design index (transistor mismatch) wherein the second design index is greater than the first design index.4. A system for high yield and speed enhancement of semiconductor integrated circuits as claimed in claim 1, wherein the delay in the two paths can be tuned by using the delay elements including one or more of a pass gate, a buffer, and a passive interconnect resistor.5. A system for high yield and speed enhancement of semiconductor integrated circuits as claimed in claim 1, wherein a 2-1 multiplexer selects one of the fast path and slow path using a SPEED control signal so that the control signal of the multiplexers in a single chip are connected together and connected to a SPEED pad.6. A system for high yield and speed enhancement of semiconductor integrated circuits as claimed in claim 1, wherein the fast path is selected when the SPEED control signal=0 and the slow path is selected when the SPEED control signal=1.7. A system for high yield and speed enhancement of semiconductor integrated circuits as claimed in claim 1, wherein after the fabrication is completed, the chips are tested at wafer level to assess if the chips are fast chips and marking a particular chip as fast if the chip is functional at SPEED=0 and slow if the chip is not functional at SPEED=0, but is functional at SPEED=1 thus dicing and separating into fast or slow bins during a packaging.8. A system for high yield and speed enhancement of semiconductor integrated circuits as claimed in claim 5, wherein for the fast chips, the SPEED pad is shorted to a GMD pad and for the slow chips, the SPEED pad is shorted to a VDD pad wherein the VDD and GND pads are adjacent to SPEED pad.9. A semiconductor memory, comprising:one or more memory cells; a sense amplifier connected to each memory cell; a firing signal circuit connected to the sense amplifier, the firing signal circuit further comprising a first input path and a second input path to a multiplexer wherein a firing signal is output from the multiplexer and is connected to the sense amplifier to trigger the sense amplifier based on one of the first and second input paths, the first input path having a first delay and the second input path having a second delay so that the memory cell is operated as one of a fast circuit using the first input path and as a slow circuit using the second input path. 10. The memory of claim 9, wherein the firing signal circuit further comprises a select signal line connected to the multiplexer that selects between the first and second input paths in order to select one of the fast circuit and the slow circuit for the memory cell operation.11. The memory of claim 9, wherein the first and second delays each further comprise a delay element that delays the signal through the first and second input paths, respectively, the delay element further comprising one of a pass gate, a buffer, and a passive interconnect resistor.12. The memory of claim 10, wherein the firing signal circuit further comprises a speed pad associated with the memory wherein the select signal line is connected to the speed pad so that a signal on the speed pad selects the first and second input paths.13. The memory of claim 12 further comprising a ground pad and a VDD pad wherein the speed pad is connected to one or the ground pad and the VDD pad to select one of the first input path and the second input path.14. A semiconductor memory sense circuit, comprising:a sense amplifier connected to a memory cell; and a firing signal circuit connected to the sense amplifier, the firing signal circuit further comprising a first input path and a second input path to a multiplexer wherein a firing signal is output from the multiplexer and is connected to the sense amplifier to trigger the sense amplifier based on one of the first and second input paths, the first input path having a first delay and the second input path having a second delay so that the memory cell is operated as one of a fast circuit using the first input path and as a slow circuit using the second input path. 15. The sense circuit of claim 14, wherein the firing signal circuit further comprises a select signal line connected to the multiplexer that selects between the first and second input paths in order to select one of the fast circuit and the slow circuit for the memory cell operation.16. The sense circuit of claim 14, wherein the first and second delays each further comprise a delay element that delays the signal through the first and second input paths, respectively, the delay element further comprising one of a pass gate, a buffer, and a passive interconnect resistor.17. The sense circuit of claim 15 further comprising a memory chip into which the sense amplifier is integrated, wherein the firing signal circuit further comprises a speed pad associated with the memory chip wherein the select signal line is connected to the speed pad so that a signal on the speed pad selects the first and second input paths.18. The sense circuit of claim 17, wherein the memory chip further comprises a ground pad and a VDD pad wherein the speed pad is connected to one or the ground pad and the VDD pad to select one of the first input path and the second input path.19. A method for selectively operating memory cells in a memory as one of a fast circuit and a slow circuit, comprising:manufacturing a memory chip having one or more memory cells, a sense amplifier connected to each memory cell and a firing signal circuit connected to the sense amplifier, the firing signal circuit further comprising a first input path and a second input path to a multiplexer wherein a firing signal is output from the multiplexer and is connected to the sense amplifier to trigger the sense amplifier based on one of the first and second input paths, the first input path having a first delay and the second input path having a second delay so that the memory cell is operated as one of a fast circuit using the first input path and as a slow circuit using the second input path; testing the memory chip to determine if each memory cell is one of a fast circuit and a slow circuit; and hardwiring a speed pad associated with the firing signal circuit to one of a ground pad and a VDD pad in order to operate each memory cell in the memory chip as one of a fast circuit and a slow circuit based on the testing so that the manufactured memory chip has both fast circuits and slow circuits.