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A method for creating a mask-programmed device from a preexisting design of a source device is provided. The method includes creating a netlist from a user defined circuit configuration file, configuring logic resources on the mask-programmed device produce basic logic elements, and generating a cus

A method for creating a mask-programmed device from a preexisting design of a source device is provided. The method includes creating a netlist from a user defined circuit configuration file, configuring logic resources on the mask-programmed device produce basic logic elements, and generating a custom interconnect based on the netlist that interconnects the configured logic resources to produce the desired logic design.

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1. A method of designing a mask-programmable device comprising:receiving a circuit configuraton file representing a circuit design; generating a netlist based on the configuration file; configuring logic resources for implementation on a base device from information in the configuration file; genera

1. A method of designing a mask-programmable device comprising:receiving a circuit configuraton file representing a circuit design; generating a netlist based on the configuration file; configuring logic resources for implementation on a base device from information in the configuration file; generating a custom interconnect design based on the netlist that interconnects the logic resources configured in the configuring step; testing for a physical design violation; and correcting the physical design violations, if any, by configuring a gate array site to function as a buffer circuit and coupling the buffer circuit to circuitry in the netlist identified as causing the physical design violation in the testing step. 2. The method of claim 1 wherein the configuring further comprise assigning certain nodes to be coupled to a logic low level based on configuration bits in the configuration file.3. The method of claim 1 wherein the configuring further comprises assigning certain nodes to be coupled to a logic high level based on configuration bits in the configuration file.4. The method of claim 1 further comprising placing at least some sections of circuitry on the netlist to corresponding sections on the mask-programmable device.5. The method of claim 4 characterized by the use of logic array blocks (LABs) as circuit sections.6. The method of claim 4 further comprising optimizing placement of the circuit sections.7. The method of claim 1 further comprising updating the netlist to include the buffer circuitry added to the circuit design in the correcting step.8. The method of claim 7 further comprising:retesting for physical design violations to determine if the correcting step corrected the physical design violation detected in the testing step; configuring additional gate array circuits to function as buffers if the retesting step reveals that additional physical design violations exist and coupling the additional buffer circuits to circuitry in the netlist identified as causing the physical design violation in the retesting step; and repeating the retesting and configuration steps until all physical design violations detected are corrected. 9. The method of claim 7 further comprising:retesting for physical design violations to determine if the correcting step corrected the physical design violations detected in the testing step; rearranging the placement of logic resources on the mask-programmable device; regenerating the interconnect; and testing again for physical design violations to determine if the rearranging and regenerating steps corrected the physical design violations detected in the retesting step. 10. A method of designing a mask-programmable device comprising:receiving a circuit configuration file representing a circuit design; generating a netlist based on the configuration file; configuring logic resources for implementation on a base device from information in the configuration file; generating a custom interconnect design based on the netlist that interconnects the logic resources configured in the configuring step; testing for Setup time violations; and correcting the Setup time violations, if any, by configuring a gate array site to function as a buffer circuit and coupling the buffer circuit to circuitry in the netlist identified as causing the Setup time violation in the testing step, wherein the receiving further comprises receiving timing information about the circuit design. 11. The method of claim 10 further comprising updating the netlist to include the buffer circuitry added to the circuit design in the correcting step.12. The method of claim 11 further comprising:retesting for Setup time violations to determine if the correcting step corrected the Setup time violation detected in the testing step; and configuring additional gate array circuits to function as buffers if the retesting step reveals that additional Setup time violations exist and coupling the additional buffer circuits to circuitry in the netlist identified as causing the Setup time violation in the retesting step; and repeating the retesting and configuration steps until all Setup time violations detected are corrected. 13. A method of designing a mask-programmable device comprising:receiving a circuit configuration file representing a circuit design; generating a netlist based on the configuration file; configuring logic resources for implementation on a base device from information in the configuration file; generating a custom interconnect design based on the netlist that interconnects the logic resources configured in the configuring step; testing for Hold time violations; and correcting the Hold time violations, if any, by configuring a gate array site to function as a delay circuit and coupling the delay circuit to circuitry in the netlist identified as causing the Hold time violation in the testing step, wherein the receiving further comprises receiving timing information about the circuit design. 14. The method of claim 13 further comprising updating the netlist to include the delay circuitry added to the circuit design in the correcting step.15. The method of claim 14 further comprising:retesting for Hold time violations to determine if the correcting step corrected the Hold time violation detected in the testing step; configuring additional gate array circuits to function as delays if the retesting step reveals that additional Hold time violations exist and coupling the additional delay circuits to circuitry in the netlist identified as causing the Hold time violation in the retesting step; and repeating the retesting and configuration steps until all Hold time violations detected are corrected. 16. A method for designing a mask-programmable logic device from a pre-existing programmable logic device circuit design comprising:receiving a configuration file representing the pre-existing programmable logic device circuit design; receiving a timing file that includes information about the timing requirements of the programmable logic device circuit design; generating a netlist based on the configuration file; creating placement information that assigns at least some sections of circuitry on the netlist to corresponding sections on the mask-programmable device; configuring logic resources for implementation on a base device from the configuration file and the placement information; and generating a custom interconnect based on the netlist that interconnects the logic resources configured in the configuring step, wherein the creating further comprises generating physical coordinate data representing specific locations on the base device. 17. The method of claim 16 wherein the configuring further comprises generating interconnection information representing how specific logic resources are interconnected to provide a logic function.18. The method of claim 16 further comprising calculating the delay associated with at least some of the circuits created by interconnecting the configured logic resources.19. The method of claim 18 further comprising comparing the timing requirements of the programmable logic device design with the delay calculated for corresponding circuits in the mask-programmable logic device to determine if there is a design violation.20. The method of claim 16, wherein the base device has at least as many logic resources and functional blocks as the pre-existing programmable logic device.21. A method for designing a mask-programmable logic device from a pre-existing programmable logic device circuit design comprising:receiving a configuration file representing the pre-existing programmable logic device circuit design; receiving a timing file that includes information about the timing requirements of the programmable logic device circuit design; generating a netlist based on the configuration file; creating placement information that assigns at least some sections of circuitry on the netlist to corresponding sections on the mask-programmable device; configuring logic resources for implementation on a base device from the configuration file and the placement information; generating a custom interconnect based on the netlist that interconnects the logic resources configured in the configuring step; calculating the delay associated with at least some of the circuits created by interconnecting the configured logic resources; comparing the timing requirements of the programmable logic device design with the delay calculated for corresponding circuits in the mask-programmable logic device to determine if there is a design violation; and correcting the design violations, if any, by configuring a gate array site to function as a buffer circuit and connecting the buffer circuit to circuitry identified as causing the Setup time violation in the testing step. 22. The method of claim 21 further comprising updating the netlist to include the buffer circuitry added to the circuit design in the correcting step.23. The method of claim 22 further comprising:testing for design violations to determine if the correcting step corrected the design violation detected in the comparing step; configuring additional gate array circuits to function as buffers if the testing step reveals that additional design violations exist and coupling the additional buffer circuits to circuitry in the netlist identified as causing the design violation in the testing step; and repeating the testing and configuration steps until all design violations detected are corrected. 24. A method for designing a mask-programmable logic device from a pre-existing programmable logic device circuit design comprising:receiving a configuration file representing the pre-existing programmable logic device circuit design; receiving a timing file that includes information about the timing requirements of the programmable logic device circuit design; generating a netlist based on the configuration file; creating placement information that assigns at least some sections of circuitry on the netlist to corresponding sections on the mask-programmable device; configuring logic resources for implementation on a base device from the configuration file and the placement information; and generating a custom interconnect based on the netlist that interconnects the logic resources configured in the configuring step, wherein the designing process causes some of the logic resources to be placed in different locations compared to the programmable logic device based on placement constraints, timing constraints, or I/O assignments. 25. The method of claim 20 wherein the logic resources comprise logic elements and logic array blocks, and wherein logic elements of the programmable logic device design are maintained in the same logic array block on the base device even though the logic array blocks are placed in different locations on the base device.26. The method of claim 24 wherein the logic resources comprise logic elements and logic array blocks, and wherein the logic elements are placed into logic array blocks that are different from the logic array blocks that the logic elements were located in on the pre-existing programmable logic device design.27. A method for designing a mask-programmable logic device from a pre-existing programmable logic device circuit design comprising:receiving a configuration file representing the pre-existing programmable logic device circuit design; receiving a timing file that includes information about the timing requirements of the programmable logic device circuit design; generating a netlist based on the configuration file; creating placement information that assigns at least some sections of circuitry on the netlist to corresponding sections on the mask-programmable device; configuring logic resources for implementation on a base device from the configuration file and the placement information; and generating a custom interconnect based on the netlist that interconnects the logic resources configured in the configuring step, wherein one base device is used to replace multiple programmable logic devices of lesser capacity. 28. A method for designing a mask-programmable logic device from a pre-existing programmable logic device circuit design comprising:receiving a configuration file representing the pre-existing programmable logic device circuit design; receiving a timing file that includes information about the timing requirements of the programmable logic device circuit design; generating a netlist based on the configuration file; creating placement information that assigns at least some sections of circuitry on the netlist to corresponding sections on the mask-programmable device; configuring logic resources for implementation on a base device from the configuration file and the placement information; and generating a custom interconnect based on the netlist that interconnects the logic resources configured in the configuring step, wherein the logic resources are arrayed on the base device in a row and column arrangement that is different than the row and column arrangement of the pre-existing programmable logic device. 29. A method for designing a mask-programmable logic device from a pre-existing programmable logic device circuit design comprising:receiving a configuration file representing the pre-existing programmable logic device circuit design; receiving a timing file that includes information about the timing requirements of the programmable logic device circuit design; generating a netlist based on the configuration file; creating placement information that assigns at least some sections of circuitry on the netlist to corresponding sections on the mask-programmable device; configuring logic resources for implementation on a base device from the configuration file and the placement information; and generating a custom interconnect based on the netlist that interconnects the logic resources configured in the configuring step, wherein the base device has at least as many logic resources and functional blocks as the pre-existing programmable logic device, and wherein the functional blocks are located in a different location base device array than on the pre-existing programmable logic device. 30. A method for designing a mask-programmable logic device from a pre-existing programmable logic device circuit design comprising:receiving a configuration file representing the pre-existing programmable logic device circuit design; receiving a timing file that includes information about the timing requirements of the programmable logic device circuit design; generating a netlist based on the configuration file; creating placement information that assigns at least some sections of circuitry on the netlist to corresponding sections on the mask-programmable device; configuring logic resources for implementation on a base device from the configuration file and the placement information; and generating a custom interconnect based on the netlist that interconnects the logic resources configured in the configuring step, wherein the logic resources comprise logic elements and logic array blocks, and wherein the logic array blocks are maintained in the same hierarchical structure as they are in the pre-existing programmable logic device design. 31. A mask-programmable logic device configured to facilitate the conversion of a source pre-existing programmable logic device design into the mask-programmable device, comprising:a base die having at least as many logic resources and functional blocks as the programmable logic device, but without the general purpose interconnection conductors of the source programmable logic device, wherein: the logic resources of the mask-programmable logic device do not include programmable elements, which causes a row-column logic array structure of the base die to be different from the row-column logic array structure of the programmable logic device, and a custom interconnect network is generated and coupled to the base die to interconnect the logic resources based on a programmable logic device conversion process. 32. The base die of claim 31, wherein the logic resources are logic array blocks, and wherein the logic array blocks on the base die have different x-y dimensions than the logic array blocks on the programmable logic device because the logic array blocks on the base die do not include programmable logic connectors.33. The base die of claim 32, wherein the row-column logic array structure of the logic resources on the base die is modified based on the different x-y dimension to maintain a relatively square die for process considerations.34. The base die of claim 31, wherein the functional blocks are in the same relative locations with respect to the logic resources as compared to the layout of the programmable logic device.35. The base die of claim 31, wherein the functional blocks on the base die are in the different relative locations with respect to the logic resources as compared to the layout of the programmable logic device.36. The base die of claim 31, wherein phase-locked loop circuitry is placed in the middle of the array to reduce noise susceptibility.