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An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A first dielectric layer on the device dielectric layer has an opening formed therein including a cond

An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A first dielectric layer on the device dielectric layer has an opening formed therein including a conductor reservoir volume. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A barrier layer lines the second channel and via opening except over the first channel opening. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via. The conductor reservoir volume provides a supply of conductor material to prevent the formation of voids in the first channel and in the via.

대표청구항 ▼

1. A method of manufacturing an integrated circuit comprising:providing a semiconductor substrate having a semiconductor device provided thereon; forming a first dielectric layer formed over the semiconductor substrate having a first opening provided therein including a conductor reservoir volume; d

1. A method of manufacturing an integrated circuit comprising:providing a semiconductor substrate having a semiconductor device provided thereon; forming a first dielectric layer formed over the semiconductor substrate having a first opening provided therein including a conductor reservoir volume; depositing a first barrier layer lining the first opening; depositing a first conductor core filling the first opening and forming a first conductor connected to the semiconductor device; forming a second dielectric layer formed over the first dielectric layer and having a via opening and a second opening provided therein; depositing a second barrier layer lining the via opening and the second opening except over the first conductor; and depositing a second conductor core filling the via and the second opening to form a via conductor and a second conductor, having the via conductor proximate the conductor reservoir volume which is at the end of the first conductor horizontally after the via conductor whereby conductor material migrates during operation due to electromigration from the conductor reservoir volume into the via conductor and second conductor wherein the volume of the conductor reservoir volume is sized to equal or exceed the volume of the via conductor. 2. The method as claimed in claim 1 wherein the depositing the barrier layer deposits a material selected from a group consisting of tantalum, titanium, tungsten, nitrides thereof, and a combination thereof.3. The method as claimed in claim 1 wherein the depositing the first and second conductor cores deposits a material selected from a group consisting of copper, copper-base alloys, aluminum, gold, gold-base alloys, silver, silver-base alloys, and a combination thereof.4. A method of manufacturing an integrated circuit comprising:providing a silicon substrate having semiconductor devices provided thereon; forming a device oxide layer formed over the silicon substrate; forming a first channel oxide layer formed over the device oxide layer having a plurality of first channel openings provided therein including a plurality of conductor reservoir volumes; depositing first barrier layers lining the plurality of first channel openings; depositing first conductor cores filling the plurality of first channel openings and forming a plurality of first channels connected to the semiconductor devices; forming a second channel oxide layer formed over the first channel oxide layer and having a plurality of second channel and via openings provided therein; depositing second barrier layers lining the plurality of second channel and via openings except over the plurality of first channels; and depositing the second conductor cores filling the plurality of second channel and via openings to form a plurality of vias and second channels, having the plurality of vias proximate the plurality of conductor reservoir volumes which are at the ends of the plurality of first channels horizontally after the plurality of vias whereby conductor material migrate in operation due to electromigration from the conductor reservoir volumes into the plurality of vias wherein the volumes of the plurality of conductor reservoir volumes are sized to equal or exceed the volumes of the vias. 5. The method of as claimed in claim 4, wherein the depositing of the barrier layer deposits a metal selected from a group consisting of tantalum, titanium, tungsten, and a combination thereof.6. The method as claimed in claim 4, wherein the depositing of the first and second conductor cores deposits a material selected from a group consisting of copper, copper-base alloys, aluminum, aluminum-base alloys, gold, gold-base alloys, silver, silver-base alloys, and a combination thereof.