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Method of forming buried conductors 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/4763
  • H01L-021/44
출원번호 US-0930521 (2001-08-15)
발명자 / 주소
  • Farrar, Paul A.
  • Noble, Wendell P.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Schwegman, Lundberg, Woessner &
인용정보 피인용 횟수 : 16  인용 특허 : 44

초록

Buried conductors within semiconductor devices and structures, and methods for forming such conductors, are disclosed. In one embodiment of the invention, a semiconductor structure includes a substrate and a plurality of conductive elements buried within the substrate. The conductive elements may be

대표청구항

1. A method comprising:forming at least one first trench within a semiconductor substrate at a first depth; depositing a first conductive material, which has a melting point high enough to prevent unwanted metallurgical changes during subsequent processing, substantially at the bottom of each first

이 특허에 인용된 특허 (44)

  1. Dingsor Andrew Dwight, Apparatus, method and article of manufacture for carrier frequency compensation in a FM radio receiver.
  2. Beyer Klaus D. (Poughkeepsie NY) Ku San-Mei (Poughkeepsie NY) Silvestri Victor J. (Hopewell Junction NY) Yapsir Andrie S. (Pleasant Valley NY), Buried air dielectric isolation of silicon islands.
  3. Esquivel Agerico L. (13912 Waterfall Way Dallas TX 75240) Mitchell Allan T. (2913 Green Meadow Garland TX 75042), Buried multilevel interconnect system.
  4. Gonzales Fernando (Boise ID), Dynamic random access memory array having a cross-point layout, tungsten digit lines buried in the substrate, and vertic.
  5. Kim Jong S. (Sungnam KRX) Yoon Hee-Koo (Seoul KRX) Choi Chung G. (Kyoungki-Do KRX), Dynamic random access memory having a vertical transistor.
  6. Yamamoto Tadashi (Kawasaki JPX) Sawada Shizuo (Yokohama JPX), Dynamic random access memory having bit lines buried in semiconductor substrate.
  7. Dubin Valery M. ; Shacham-Diamand Yosef ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K., Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications.
  8. Lee Kyu-Woong (Arlington MA) Durschlag Mark S. (Natick MA) Day John (Lexington MA), Evaporated thick metal and airbridge interconnects and method of manufacture.
  9. Pluymers Brian Alan ; Nixon Doreen Marie, Fabrication of a circuit module with a coaxial transmission line.
  10. Saia Richard Joseph ; Durocher Kevin Matthew ; Cole Herbert Stanley, Flexible interconnect film including resistor and capacitor layers.
  11. Farrar Paul A. ; Forbes Leonard, High-Q inductive elements.
  12. Paul A. Farrar ; Leonard Forbes, High-Q inductive elements.
  13. Paul A. Farrar ; Leonard Forbes, High-Q inductive elements.
  14. Prasad Jayasimha S. (Tigard OR) Park Song W. (Aloha OR) Vetanen William A. (Sherwood OR) Beers Irene G. (Sherwood OR) Haynes Curtis M. (Portland OR), Implant-free heterojunction bioplar transistor integrated circuit process.
  15. Dobrovolny Pierre (North Riverside IL), Integrated RF receiver/waveguide.
  16. Grzegorek Andrew Z. ; McFarland William J., Integrated circuit compatible planar inductors with increased Q.
  17. Oppermann Klaus-Guenter,DEX, Integrated circuit structure with interconnect formed along walls of silicon island.
  18. Kuhn William B. ; Riad Aicha-Elshabini ; Stephenson William F., Interwound center-tapped spiral inductor.
  19. Beyer Klaus D. (Poughkeepsie NY) Silvestri Victor J. (Hopewell Junction NY) Yapsir Andrie S. (Pleasant Valley NY), Isolated films using an air dielectric.
  20. Lund Clarence A. (Phoenix AZ) Sugino Michael D. (Mesa AZ), Low resistance buried power bus for integrated circuits.
  21. Noble Wendell, Memory array having a digit line buried in an isolation region and method for forming same.
  22. Houston Theodore W. (Richardson TX), Method for forming a semiconductor on insulator device.
  23. Farrar Paul A. ; Forbes Leonard, Method for making high-Q inductive elements.
  24. Gaul Stephen Joseph (Melbourne FL), Method of bonding wafers having vias including conductive material.
  25. Klatskin Jerome Barnard (Princeton Junction NJ) Rosen Arye (Cherry Hill NJ), Method of electrically interconnecting semiconductor elements.
  26. Tam Gordon (Chandler AZ) Granick Lisa R. (Philadelphia PA), Method of fabricating airbridge metal interconnects.
  27. Yang Ming-Tzong (Hsin-Chu TWX) Hong Gary (Hsin-Chu TWX), Method of fabrication of MOSFET device with buried bit line.
  28. Liu Chung-Shi,TWX ; Yu Chen-Hua,TWX, Method of forming a smooth copper seed layer for a copper damascene structure.
  29. Chen Fusen E. (Dallas TX) Liou Fu-Tai (Carrollton TX) Dixit Girish A. (Dallas TX), Method of forming vias.
  30. Grader Gideon S. (Haifa NJ ILX) Johnson ; Jr. David W. (Pluckemin NJ) Roy Apurba (Rockwall TX) Thomson ; Jr. John (Spring Lake NJ), Method of making a multilayer monolithic magnet component.
  31. Chino Toyoji (Osaka JPX) Matsuda Kenichi (Osaka JPX) Shibata Jun (Osaka JPX), Method of making semiconductor device with air-bridge interconnection.
  32. Cha Sung W. (Cambridge MA) Suh Nam P. (Sudbury MA) Baldwin Daniel F. (Medford MA) Park Chul B. (Cambridge MA), Microcellular thermoplastic foamed with supercritical fluid.
  33. Nakano Hirofumi (Itami JPX), Multi-layer wiring.
  34. Miura Takao,JPX ; Yamauchi Tunenori,JPX ; Monma Yoshinobu,JPX ; Goto Hiroshi,JPX, Process for manufacturing semiconductor devices separated by an air-bridge.
  35. Gardner Donald S., Process of fabricating embedded ground plane and shielding structures using sidewall insulators in high frequency circu.
  36. Klose Helmut,DEX ; Weber Werner,DEX ; Bertagnolli Emmerich,DEX ; Koppe Siegmar,DEX ; Hubner Holger,DEX, Semiconductor component for vertical integration and manufacturing method.
  37. Buti Taqi N. (Millbrook NY) Hsu Louis L. (Fishkill NY) Joshi Rajiv V. (Yorktown Heights NY) Shepard Joseph F. (Hopewell Junction NY), Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding.
  38. Ohya Shuichi,JPX ; Sakao Masato,JPX ; Takaishi Yoshihiro,JPX ; Kajiyana Kiyonori,JPX ; Akimoto Takeshi,JPX ; Oguro Shizuo,JPX ; Shishiguchi Seiichi,JPX, Semiconductor memory device having trench isolation regions and bit lines formed thereover.
  39. Baldwin Daniel F. (Medford MA) Suh Nam P. (Sudbury MA) Park Chul B. (Cambridge MA) Cha Sung W. (Cambridge MA), Supermicrocellular foamed materials.
  40. Bertin Claude L. (South Burlington VT) Farrar ; Sr. Paul A. (South Burlington VT) Kalter Howard L. (Colchester VT) Kelley ; Jr. Gordon A. (Essex Junction VT) van der Hoeven Willem B. (Jericho VT) Whi, Three dimensional multichip package methods of fabrication.
  41. Bertin Claude L. (South Burlington) Farrar ; Sr. Paul A. (South Burlington) Kalter Howard L. (Colchester) Kelley ; Jr. Gordon A. (Essex Junction) van der Hoeven Willem B. (Jericho) White Francis R. (, Three-dimensional multichip packages and methods of fabrication.
  42. Kenney Donald M. (Shelburne VT), Trench interconnect for CMOS diffusion regions.
  43. Okumura Yoshinori (Hyogo JPX), Trench type semiconductor memory device having side wall contact.
  44. Lu Chih-Yuan (Hsin-chu TWX), Vertical DRAM cross point memory cell and fabrication method.

이 특허를 인용한 특허 (16)

  1. Nejad, Hasan; Figura, Thomas A.; Haller, Gordon A.; Iyer, Ravi; Meldrim, John Mark; Harnish, Justin, Method of forming a transistor gate of a recessed access device, method of forming a recessed transistor gate and a non-recessed transistor gate, and method of fabricating an integrated circuit.
  2. Chopra,Dinesh; Donohoe,Kevin G.; Basceri,Cem, Method of providing a structure using self-aligned features.
  3. Gordon, Haller A.; Sanh, Tang D.; Steven, Cummings, Methods of fabricating a memory device.
  4. Haller, Gordon; Tang, Sanh D.; Cummings, Steve, Methods of fabricating a memory device.
  5. Haller, Gordon; Tang, Sanh Dang; Cummings, Steve, Methods of fabricating a memory device.
  6. Figura, Thomas Arthur; Haller, Gordon A., Peripheral gate stacks and recessed array gates.
  7. Forbes, Leonard; Farrar, Paul A.; Bhattacharyya, Arup; Hanafi, Hussein I.; Farnworth, Warren M., Semiconductor devices.
  8. Alptekin, Emre; Batra, Pooja R.; Cheng, Kangguo; Divakaruni, Ramachandra; Faltermeier, Johnathan E.; Vega, Reinaldo A., Semiconductor structure having buried conductive elements.
  9. Alptekin, Emre; Batra, Pooja R.; Cheng, Kangguo; Divakaruni, Ramachandra; Faltermeier, Johnathan E.; Vega, Reinaldo A., Semiconductor structure having buried conductive elements.
  10. Nejad, Hasan; Figura, Thomas A.; Haller, Gordon A.; Iyer, Ravi; Meldrim, John Mark; Harnish, Justin, Silicided recessed silicon.
  11. Nejad, Hasan; Figura, Thomas A.; Haller, Gordon A.; Iyer, Ravi; Meldrim, John Mark; Harnish, Justin, Silicided recessed silicon.
  12. Ding, Hanyi; Erturk, Mete; Groves, Robert A.; He, Zhong-Xiang; Lindgren, Peter J.; Stamper, Anthony K., Structure and design structure for high-Q value inductor and method of manufacturing the same.
  13. Ding, Hanyi; Erturk, Mete; Groves, Robert A.; He, Zhong-Xiang; Lindgren, Peter J.; Stamper, Anthony K., Structure and design structure for high-Q value inductor and method of manufacturing the same.
  14. Levy, Max G.; Voldman, Steven H., Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applications.
  15. Levy, Max G.; Voldman, Steven H., Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applications.
  16. Levy, Max G.; Voldman, Steven H., Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applications.
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