초록 ▼

A data transceiving station of digital data frames includes a digital modem coupled to a transmission line, and a microprocessor receiving demodulated data from the modem according to a Packet Mode or a Bit Mode transmission through an interface circuit. The interface circuit switches between the Pa

A data transceiving station of digital data frames includes a digital modem coupled to a transmission line, and a microprocessor receiving demodulated data from the modem according to a Packet Mode or a Bit Mode transmission through an interface circuit. The interface circuit switches between the Packet Mode and the Bit Mode transmission during transfer of a data frame to the microprocessor. The data transceiving station combines the superior speed of a Packet Mode transfer with the unlimited compatibility of a Bit Mode transfer.

대표청구항 ▼

1. A data transceiver station comprising:a modem to be connected to an electrical power line for receiving digital data;a microprocessor connected to said modem for receiving demodulated digital data therefrom according to a Packet Mode transmission or a Bit Mode transmission; andan interface circui

1. A data transceiver station comprising:a modem to be connected to an electrical power line for receiving digital data;a microprocessor connected to said modem for receiving demodulated digital data therefrom according to a Packet Mode transmission or a Bit Mode transmission; andan interface circuit connected between said microprocessor and said modem and switching between a Packet Mode and a Bit Mode during transfer of the demodulated digital data to said microprocessor, the switching being based upon whether the received digital data is a Packet Mode transmission or a Bit Mode transmission.2. A data transceiver station according to claim 1 wherein the electrical power line is part of an electrical power distribution network; and wherein said modem generates information on detection of a voltage level greater than a threshold in a frequency band selected for transmission over the electrical power line.3. A data transceiver station according to claim 2 further comprising a zero-crossing circuit for detecting a zero-crossing of the voltage level and for producing a logic signal in response thereto that is input to said modem.4. A data transceiver station according to claim 1 wherein said serial interface comprises a receiver section and a transmitter section connected thereto, said transmitter section comprising:a logic processing circuit for organizing the demodulated digital data into a stream of data structured in packets, anda multiplexer having a first input for receiving the demodulated digital data and a second input for receiving the stream of data structured in packets, and an output for providing the demodulated digital data or the stream of data structured in packets based upon a selection signal.5. A data transceiver station according to claim 1 further comprising an oscillator connected to said modem for providing carrier frequencies thereto.6. A data transceiver station according to claim 4 further comprising a memory connected to said logic processing circuit.7. A data transceiver station according to claim 4 wherein said logic processing circuit has an input for receiving a first clock signal corresponding to the demodulated digital data; and wherein said logic processing circuit provides a third clock signal comprising a sequence of N pulses having a second clock signal that is a multiple of a frequency of the first clock signal.8. A data transceiver station according to claim 4 wherein said multiplexer has a third input for receiving the first clock signal and a fourth input for receiving a fourth clock signal equal to the third clock signal or to the first clock signal based upon whether the selection signal corresponds to the demodulated digital data or the stream of data structured in packets.9. A data transceiver station according to claim 4 further comprising a memory connected to said logic processing circuit, wherein said memory comprises:a first register having a first input for receiving the demodulated digital data and a second input for receiving a first register clock signal, and an output for providing a first data signal; anda second register having a first input for receiving the demodulated digital data and a second input for receiving a second register clock signal, and an output for providing a second data signal.10. A data transceiver station according to claim 9 wherein said logic processing circuit further comprises:a first counter having an input for receiving the first clock signal and an output for providing a first end-computation signal when N pulses have been counted; anda second counter having an input for receiving a second clock signal, and an output for providing a second end-computation signal that is enabled by the first end-computation signal and disabled when said second counter counts N pulses of the second clock signal.11. A data transceiver station according to claim 9 wherein said logic processing circuit further comprises:a second multiplexer having a first input for receiving the demodulated digital data and a second input for receiving the third clock signal, and an output for providing the first register clock signal corresponding alternately to the third clock signal and to the first clock signal based upon a switching signal that toggles every N pulses of the first clock signal; anda third multiplexer having a first input for receiving the demodulated digital data and a second input for receiving the third clock signal, and an output for providing the second register clock signal corresponding alternately to the third clock signal and to the first clock signal based upon the switching signal.12. A data transceiver station according to claim 11 wherein said logic processing circuit further comprises a logic AND gate having a first input for receiving the second clock signal and a second input for receiving the second end-computation signal, and an output for providing the third clock signal as periodic sequences of the N pulses when the second clock signal is output at each enablement of the first end-computation signal.13. A data transceiver station according to claim 12 wherein said logic processing circuit further comprises a fourth multiplexer having a first input for receiving the first data signal and a second input for receiving the second data signal, and an output for providing a third data signal corresponding to the first data signal or to the second data signal based upon the switching signal.14. A data transceiver station according to claim 1 wherein said modem comprises at least one control register for storing the received digital data and for controlling verification thereof.15. A data transceiver station according to claim 1 wherein the demodulated digital data is based upon frequency shift keying demodulation.16. A monolithic integrated multichannel transceiver comprising:a modem having an input to be connected to an electrical power line of an electrical distribution power network for receiving digital data and an output for providing a demodulated bit stream in response to the received digital data, said modem for detecting a voltage level in a frequency band selected for transmission over the electrical power line and for providing a logic signal when the voltage level exceeds a threshold;a serial interface connected to said modem for providing a selection signal based upon the received digital data, said serial interface comprising a receiver section and a transmitter section connected thereto, said transmitter section comprisinga logic processing circuit for organizing the demodulated bit stream into a stream of data structured in packets, anda multiplexer having a first input for receiving the demodulated bit stream and a second input for receiving the stream of data structured in packets, and an output for providing the demodulated bit stream or the stream of data structured in packets based upon the selection signal; anda zero-crossing circuit connected to an external coupling circuit connected to the electrical power line for detecting a zero-crossing of the voltage level thereon and for providing an output logic signal to said modem in response to the zero-crossing of the voltage level.17. A monolithic integrated multichannel transceiver according to claim 16 wherein the demodulated bit stream corresponds to a Bit Mode transmission and the stream of data structured in packets corresponds to a Packet Mode transmission.18. A monolithic integrated multichannel transceiver according to claim 16 wherein said modem comprises at least one control register for storing the received digital data and for controlling verification thereof.19. A monolithic integrated multichannel transceiver according to claim 16 further comprising an oscillator connected to said modem for providing carrier frequencies thereto.20. A monolithic integrated multichannel transceiver according to claim 16 further comprising a memory connected to said logic processing circuit.21. A monolithic integrated multichannel transceiver according to claim 16 further comprising a power interface circuit connected to said modem and for driving the external coupling circuit.22. A monolithic integrated multichannel transceiver according to claim 16 wherein said logic processing circuit has an input for receiving a first clock signal corresponding to the demodulated bit stream; and wherein said logic processing circuit provides a third clock signal comprising a sequence of N pulses having a second clock signal that is a multiple of a frequency of the first clock signal.23. A monolithic integrated multichannel transceiver according to claim 16 wherein said multiplexer has a third input for receiving the first clock signal and a fourth input for receiving a fourth clock signal equal to the third clock signal or to the first clock signal based upon whether the selection signal corresponds to the demodulated bit stream or the stream of data structured in packets.24. A monolithic integrated multichannel transceiver according to claim 16 further comprising a memory connected to said logic processing circuit, wherein said memory comprises:a first register having a first input for receiving the demodulated bit stream and a second input for receiving a first register clock signal, and an output for providing a first data signal; anda second register having a first input for receiving the demodulated bit stream and a second input for receiving a second register clock signal, and an output for providing a second data signal.25. A monolithic integrated multichannel transceiver according to claim 24 wherein said logic processing circuit further comprises:a first counter having an input for receiving the first clock signal and an output for providing a first end-computation signal when N pulses have been counted; anda second counter having an input for receiving a second clock signal, and an output for providing a second end-computation signal that is enabled by the first end-computation signal and disabled when said second counter counts N pulses of the second clock signal.26. A monolithic integrated multichannel transceiver according to claim 24 wherein said logic processing circuit further comprises:a second multiplexer having a first input for receiving the demodulated bit stream and a second input for receiving the third clock signal, and an output for providing the first register clock signal corresponding alternately to the third clock signal and to the first clock signal based upon a switching signal that toggles every N pulses of the first clock signal; anda third multiplexer having a first input for receiving the demodulated bit stream and a second input for receiving the third clock signal, and an output for providing the second register clock signal corresponding alternately to the third clock signal and to the first clock signal based upon the switching signal.27. A monolithic integrated multichannel transceiver according to claim 25 wherein said logic processing circuit further comprises a logic AND gate having a first input for receiving the second clock signal and a second input for receiving the second end-computation signal, and an output for providing the third clock signal as periodic sequences of the N pulses when the second clock signal is output at each enablement of the first end-computation signal.28. A monolithic integrated multichannel transceiver according to claim 26 wherein said logic processing circuit further comprises a fourth multiplexer having a first input for receiving the first data signal and a second input for receiving the second data signal, and an output for providing a third data signal corresponding to the first data signal or to the second data signal based upon the switching signal.29. A method of using a data transceiver station for exchanging digital data over an electrical power line, the data transceiver station comprising a modem connected to the electrical power line, an interface circuit connected to the modem, and a microprocessor connected to the interface circuit, the method comprising:demodulating the digital data using the modem;switching the interface circuit between a Packet Mode and a Bit Mode based upon whether the received digital data is a Packet Mode transmission or a Bit Mode transmission; andtransferring the demodulated digital data from the modem to the microprocessor.30. A method according to claim 29 wherein demodulating the digital data comprises providing a demodulated bit stream to the serial interface.31. A method according to claim 30 further comprising organizing the demodulated bit stream into a stream of data structured in packets.32. A method according to claim 31 further comprising providing to a first input of a multiplexer the demodulated bit stream and to a second input of the multiplexer the stream of data structured in packets, and providing at an output of the multiplexer the demodulated bit stream or the stream of data structured in packets based upon a selection signal.33. A method according to claim 32 further comprising generating the selection signal based upon the received digital data.34. A method according to claim 29 further comprising:detecting a zero-crossing of a voltage level on the electrical power line; andproviding an output logic signal to the modem in response to the zero-crossing of the voltage level.35. A method according to claim 29 further comprising:detecting a voltage level in a frequency band selected for transmission over the electrical power line; andproducing a logic signal when the voltage level exceeds a threshold.36. A method according to claim 29 wherein the modem comprises at least one control register for storing the digital data and for controlling verification thereof.